Abstract: Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.

Abstract: Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.

Abstract: A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).

Abstract: In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.

Abstract: Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

Abstract: A debugging device for performing a debugging process through an electronic device external connector system is provided. The debugging device performs the debugging process to a target system, and the device comprises a first external connector, a switch, and a debugging module. The first external connector is connected to the external port of the target system. The switch is connected to the first external connector, and the switch chooses to activate the debugging process. The debugging module is connected to the switch, and the debugging module receives a universal asynchronous receiver/transmitter (UART) signal provided by the target system.

Abstract: Embodiments are directed to a method of embedding configuration files in a document generated by a system, with the configuration file including settings associated with the generation of the document. A particular embodiment is directed to the embedding of configuration files of a testing system in a report document generated by the testing system. The configuration file includes system settings and external settings in association with the test results documented in the report document. For example, a testing system can generate a PDF report document associated with a test performed, and embed configuration files into the PDF report document. The embedding of configurations files in the PDF document can be done by using standard embedding mechanisms already available in the PDF file format and supported by most PDF viewing tools. The embedding of the configuration file can be performed automatically when the report document is generated.

Abstract: A DDR signal testing assistant device includes a body. The body is detachably locked to a motherboard integrated with a DDR connector. The DDR connector defines a plurality of pins. The body defines a plurality of testing holes corresponding and mating with the pins. Each testing hole of the body is marked with characters. The characters indicate the denomination or property of each corresponding pin of the DDR connector.

Abstract: A test system includes a motherboard and a test card. The motherboard includes a number of electronic components and a first connector. The test card includes a second connector and a number of indicating circuits. The first connector includes a number of signal pins. Each signal pin of the first connector is connected to a corresponding signal terminal of the electronic components, to receive a power good signal. The second connector includes a number of signal pins. Each signal pin of the second connector is connected to a corresponding signal pin of the first connector, to receive a corresponding power good signal. Each indicating circuit is connected to a corresponding signal pin of the second connector, and indicates whether the corresponding signal pin of the second connector outputs a power good signal.

Abstract: A testing device communicating with an input device is capable of executing a plurality of programs. The testing device includes a displaying unit, a detecting unit, and a judging unit. The displaying unit displays the working windows of the executing program in an overlapping manner. The detecting unit detects whether a controlling signal corresponding to a predetermined program of the testing device is received from the input device. The judging unit judges whether the working window of the predetermined program is the top-level working window in response to the controlling signal and switches the working window of the predetermined program to be the top-level working window when the working window of the predetermined program is not the top-level working window.

Abstract: An apparatus for testing a basic input output system (BIOS) chip includes a base and a connector. The base defines a receiving space for housing the BIOS chip. A number of signal pins are formed on sidewalls bounding the receiving space, to electrically connect the BIOS chip. The connector extends from a bottom of the base, and is electrically connected to the signal pins of the base to be connected to a diagnose card to debug the BIOS chip.

Abstract: In a test data management method, an electronic signal that needed to be tested of an electronic device is select. A predefined template file of a test report of the electronic signal is generated. Test data of the electronic signal is obtained from a test file, and is inserted into predetermined locations of the template file. The test report of the electronic signal is generated according to the template file and the inserted test data, and the test report is stored into a storage system of a computing device.

Abstract: A test apparatus comprising a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

Abstract: A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus includes a data store for storing a current debug exception mask value. The data processing circuitry is configured to set the mask value to a first value in the data store in response to executing critical code and on termination of execution of the critical code to reset the mask value to not store the first value. The data processing circuitry is configured, in response to receipt of a control signal indicating a debug exception is to be taken, to allow the exception to be taken if the mask value is not set to the first value and not to allow said exception to be taken if the mask value is set to the first value.

Abstract: A server includes a baseboard management controller (BMC). More than one inter-integrated circuit (I2C) device may be connected to the BMC via a multiplexing switch. The server sets a first identifier for indicating which channels of I2C device are open, and a second identifier for indicating which channels of the I2C devices are closed, and sends the set information to the BMC. To test a selected I2C device, the server opens a channel to the selected I2C device and assigns the first identifier to the channel of the selected I2C device. During testing of the selected I2C device, if the BMC intends to access a different I2C device, the BMC waits for the identifier of the selected I2C device to change from the first identifier to the second identifier, and then opens a channel to the different I2C device.

Abstract: A computer implemented system for testing electronic equipment where test inputs, test outputs, test applied environmental conditions, and test processes are recorded and correlated.

Abstract: Wrapper cells for simultaneous testing of parent functional elements and child functional elements in a hierarchical SoC (System on Chip) provide a substantially reduced integrated circuit footprint by eliminating a multiplexer and providing simpler interconnections. Identical wrapper cells may be used for input and output data lines reducing the cost of the cell library.

Abstract: A method and system for providing on-product clocks for domains compatible with compression is disclosed. According to one embodiment, a base signal received from automated test equipment has a frequency for testing a plurality of clock domains and programming instruction for first and second clock domains of a plurality of clock domains. First and second clock signals are generated from the base clock signal based on the programming instruction. A first delay for the first clock signal and a second delay for the second clock signal are determined from the programming instruction. A test sequence is provided to test a first clock domain and a second clock domain. The test sequence comprises the first clock signal delayed by the first delay and the second clock signal delayed by the second delay. The first clock drives the first clock domain and the second clock derives the second clock domain.

Abstract: According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.

Abstract: Method and structures provide for testing a SAS link during speed negotiation windows to determine success/failure in using a negotiated speed at one or more configured sets of speed options. For each device linked to a master SAS device, each possible set of speed options is configured; the device participates in a speed negotiation window operation with the current speed options configured. One or more SCSI requests are forwarded from the master device to the attached device. The SCSI requests may be non-destructive of data stored on the attached device. Results of the tests may be used to select a preferred speed for communication between the master device and that attached device. The speed options to be varied and tested may include: link speed; spread spectrum clocking for each SAS speed; type of supported spread spectrum clocking; and logical link rate in support of multiplexing.

Abstract: A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.

Abstract: Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data.

Abstract: Described embodiments provide a media controller for processing a diagnostic request received from a diagnostic source. The received diagnostic request is parsed by a corresponding request handling module of the media controller, where each diagnostic source type has a corresponding request handling module. If the received diagnostic request requires allocation of buffer space, a common diagnostic handling module of the media controller allocates buffer space in a buffer for the received diagnostic request. The common diagnostic handling module is common for all diagnostic source types. The common diagnostic handling module provides the received diagnostic request to a corresponding one of a plurality of end diagnostic handling modules. The end diagnostic handling module performs the diagnostic tasks. If the received diagnostic request requires a transfer of data to the diagnostic source, the common diagnostic handling module performs the data transfer between the media controller and the diagnostic source.

Abstract: A computer system on/off test apparatus includes a time control unit receiving a time interval value and a repetition value, a detecting unit detecting signal parameters of the computer system, and a test control unit receiving an external power supply and switching the power connection between the external power supply and the computer system. The test control unit saves a number of acceptable ranges. The test control unit receives a power-on status signal returned from the computer system in response to the computer system is powered. The test control unit determines whether the power-on status signal is correct and the detected signal parameters of the computer system are within the acceptable ranges correspondingly. The test control unit turns off the computer system after the interval time, and then turns on the computer system to repeat the above process until the test number of tests reaches the repetition value.

Abstract: A testing apparatus includes a vector memory unit storing original test vector data in which an input signal to be inputted to a circuit subjected to inspection is described, a vector generator generating generated test vector data from the original test vector data, an output part outputting test vector data to be inputted to the inspected circuit, a fault occurrence rate memory unit storing a fault occurrence rate of the input signal, a random number generator generating random number data, and a comparison part comparing the fault occurrence rate of the input signal with the random number data. The vector output part outputs the generated test vector data when the random number data is smaller than the fault occurrence rate of the input signal, and outputs the original test vector data when the random number data is larger than the fault occurrence rate of the input signal.

Abstract: A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.

Abstract: A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

Abstract: A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Abstract: A test system includes a host, a module to communicate with the host, and a test device to test the module while the module is connected to the host. The host includes a pulse width modulator circuit to supply a power to the module, and the test device varies a feedback resistance value provided to the pulse width modulator circuit.

Abstract: A semiconductor integrated circuit comprises a plurality of cores (99) connected with an inter-connection network (1000) and a test controller (500) which is connected with the inter-connection network (1000) and which issues a test control request associated with the test of the core (99) via the inter-connection network (1000). The inter-connection network (1000) is constituted of a plurality of adapters (3000) which serve as connection interfaces of the plurality of cores (99) and the test controller (500), respectively, and a plurality of routers (2000) which connect the plurality of adapters (3000). The adapters (3000) connected with the core (99) comprise a core testing unit for vicariously testing core (99) connected to itself based on the test control request received from the test controller (500) via the inter-connection network (1000).

Abstract: A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.

Abstract: An integrated circuit chip includes a plurality of two-way transceivers capable of simultaneously transmitting and receiving signals, a switch circuit coupled to the plurality of two-way transceivers and to a given node to provide switchable couplings between the plurality of two-way transceivers and the given node, an interconnection information storage unit to store interconnection information, and a control circuit to set the couplings of the switch circuit in response to the interconnection information.

Abstract: A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for sending test signals to the input interface and receiving feedback signals from the output interface for facilitating locating and recording errors during testing of the computer. A testing method for testing the computer is also disclosed.

Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.

Abstract: An error detection method for a computer system includes the steps of: enabling an error-detecting computer to communicate with a keyboard controller of a computer-under-test through a communication interface; enabling the error-detecting computer to issue an error detection command to the keyboard controller that causes the keyboard controller to issue a request command to the basic input/output system (BIOS) of the computer-under-test; enabling the BIOS, in response to the request command, to access the keyboard controller and determine hardware status information that is being requested from the error detection command, and subsequently, to obtain the hardware status information of the computer-under-test, and to transmit the hardware status information to the keyboard controller; and enabling the keyboard controller to transmit the hardware status information received thereby to the error-detecting computer through the communication interface.

Abstract: A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals.

Abstract: A testing device for a USB I/O board includes USB plugs connected to the USB I/O board, a connector connected to the USB I/O board, an indication module, and a testing module including data output terminals connected to the USB plugs, data reception terminals connected to the connector, and indication terminals connected to the indication module. The testing module sends a testing signal to the USB I/O board via the data output terminals, and receives the testing signal from the USB I/O board via the data reception terminals. The testing module compares the testing signal to a threshold signal stored in the testing module. If the testing signal and the threshold signal are not substantially the same, the testing module generates an alarm signal to drive the indication module via the indication terminal. The indication module indicates the USB I/O board is abnormal.

Abstract: An exemplary motherboard tester includes a processor comprising a pair of data terminals for transmitting data; and an interface comprising: a pair of data terminals coupled to the data terminals of the processor respectively; at least one output terminal arranged for connecting to a corresponding pin of a chipset mounted on a motherboard to send a test signal generated by the processor to the pin; and at least one input terminal arranged for connecting to a test point on the motherboard which is electrically connected to the pin, to receive a feedback signal from the test point, wherein, the processor compares the feedback signal with the test signal to determine whether the pin of the chipset is normal, open, or shorted.

Abstract: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Abstract: An MC 10 includes a universal asynchronous receiver transceiver UART as a communication circuit. A tester (6) includes a serial communication interface (61). By serial communication between these two, the operation of an electronic unit 1 is tested. A common output circuit (31) is provided as an output circuit of the UART 11. This common output circuit (31) is a circuit which doubles as one of output circuits of the MC 10, one end thereof is connected to a UART port and another general port of the MC 10 and the other end thereof is connected to a terminal connected to a load (7).

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.