With Comparison Between Actual Response And Known Fault-free Response, E.g., Signature Analyzer, Etc. (epo) Patents (Class 714/E11.175)
  • Publication number: 20130111283
    Abstract: A system for testing a plurality of memories includes a plurality of memory testing devices and a controller. Each of the memory testing devices is coupled to one of the memories. The controller is configured to generate a test vector and send the test vector to the memory testing devices. Each of the memory testing devices tests its coupled memory respectively according to the test vector and sends a test result to the controller.
    Type: Application
    Filed: October 1, 2012
    Publication date: May 2, 2013
    Applicant: O2Micro Inc.
    Inventor: O2Micro Inc.
  • Publication number: 20130091394
    Abstract: A data processing apparatus includes a ROM (Read Only Memory) having a validity verification program stored therein, an auxiliary storage device including a plurality of storage areas having a plurality of target verification data stored therein, an execution unit configured to perform a validity verification process on the plural target verification data in accordance with the validity verification program. An order of priority is assigned to the plural target verification data. The plural storage areas have addresses that is recognizable by the execution unit. The execution unit is configured to determine validity of each of the plural target verification data based on the order of priority until one of the plural target verification data is determined to be valid.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 11, 2013
    Inventor: Kei KATO
  • Publication number: 20110173496
    Abstract: A system for condition monitoring and fault diagnosis includes a data collection function that acquires time histories of selected variables for one or more of the components, a pre-processing function that calculates specified characteristics of the time histories, an analysis function for evaluating the characteristics to produce one or more hypotheses of a condition of the one or more components, and a reasoning function for determining the condition of the one or more components from the one or more hypotheses.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 14, 2011
    Applicant: BROOKS AUTOMATION, INC.
    Inventors: Martin Hosek, Jay Krishnasamy, Jan Prochazka
  • Publication number: 20090222694
    Abstract: Device, system and method for verification of a hardware system-under-test including at least one processor. A method includes building an executable image of a hardware exerciser adapted for execution on a test platform selected from: a simulation accelerator, a hardware emulator, a prototype hardware system, and a hardware production wafer. The exerciser image includes embedded data corresponding to architectural knowledge, testing knowledge, and a test template. The test template is defined in a context-free formal language and includes biasing directives to influence at least one of a desired test structure, one or more resources to be included in the test, and one or more values of the included resources. The architectural knowledge is obtained from an architectural model including a formal description of the specification for the system-under-test, and the testing knowledge is obtained from a testing knowledgebase including heuristics for testing desired aspects of the system-under-test.
    Type: Application
    Filed: February 28, 2008
    Publication date: September 3, 2009
    Inventors: Allon Adir, Gil Eliezer Shurek
  • Publication number: 20090138759
    Abstract: A method and a computing system for performing the method. Microstates of components of a computing system are organized into macrostates of the computing system. Each microstate represents a state that a component of the computing system is able to individually enter. Each macrostate represents a state that the computing system is able to enter as a whole. The macrostates of the computing system are organized into meta-dynamic states of the computing system. The computing system is monitored such that perturbations of the computing system are detected, wherein a perturbation of the computing system will result in movement thereof to a new meta-dynamic state. It is determined that the new meta-dynamic state is undesirable. A path is determined. The path causes the computing system to move back to a desirable meta-dynamic state. The computing system is caused to move on the path to the desirable meta-dynamic state.
    Type: Application
    Filed: January 23, 2009
    Publication date: May 28, 2009
    Inventor: Deepak K. Gangadhar
  • Publication number: 20080307275
    Abstract: Provided are a method and system checking output from multiple execution units. Execution units concurrently execute test instructions to generate test output, wherein test instructions are transferred to the execution units from a cache coupled to the execution units over a bus. The test output from the execution units is compared to determine whether the output from the execution units indicates the execution units are properly concurrently executing test instructions. The result of the comparing of the test output are forwarded to a design test unit.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: Allan WONG, Lance CHENEY
  • Publication number: 20080288836
    Abstract: In a test mode, a comparator compares for each column a value of data read from each memory cell connected to an activated word line with an expected value to be read from each memory cell. An error register holds error data based on a comparison result by a comparator. Each bit of the error data indicates the comparison result by the comparator for a corresponding column. Each bit is set to “0” when the comparison result for the corresponding column always indicates equality whichever word line is activated, and is set to “1” when once the comparison result for the corresponding column indicates difference.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 20, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Soichi Kobayashi, Yoshiaki Yamazaki, Yukihiko Shimazu
  • Publication number: 20080104458
    Abstract: A plurality of test patterns generated by a test pattern generator is output from a first memory chip to test a second memory chip, which is of a different type from the first memory chip and mounted in the same package. Therefore, when different types of memory chips are mounted in the same package, the memory chip is tested even no terminal of the memory chip is connected to an external terminal of a system. Since there is no need to form any useless terminal in the system, system cost is reduced. Since a testing apparatus generating complicated test patterns is made unnecessary, test cost is reduced. The test pattern generator is constructed using nonvolatile logic and therefore, tests can be carried out without preparing test patterns in advance. Consequently, a user who purchases the first and second memory chips to construct a system can also carry out tests easily.
    Type: Application
    Filed: October 19, 2007
    Publication date: May 1, 2008
    Inventor: Toshiya Uchida
  • Publication number: 20080082871
    Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).
    Type: Application
    Filed: September 28, 2007
    Publication date: April 3, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoe-ju CHUNG, Yun-sang LEE
  • Publication number: 20080052584
    Abstract: There is provided a test apparatus for testing a semiconductor device. The test apparatus includes a pattern generating section that sequentially reads and outputs waveform information to be used for testing the semiconductor device, where the waveform information is made up by a plurality, of pieces of data, a waveform generating section that generates a waveform based on the waveform information which is sequentially output from the pattern generating section, a match detecting section that detects, in response to a signal indicating a match detection request cycle output from the pattern generating section, whether an output signal output from the semiconductor device matches an expected value pattern, and an interrupt section that, when the match detecting section detects that the output signal matches the expected value pattern, terminates the match detection request cycle and causes the pattern generating section to output next waveform information.
    Type: Application
    Filed: February 9, 2007
    Publication date: February 28, 2008
    Applicant: Advantest Corporation
    Inventor: Masaru Doi
  • Publication number: 20080034265
    Abstract: A tester for testing a semiconductor device is disclosed. In accordance with the tester, a data is fetched using a data strobe signal transmitted from a DUT, thereby increasing an accuracy of the fetched data, securing a window for fetching a last portion of the data using a data strobe enable signal and efficiently compensating for a round trip delay of an expected data without using the deskew component.
    Type: Application
    Filed: July 25, 2007
    Publication date: February 7, 2008
    Applicant: Unitest Inc.
    Inventor: Jong Koo KANG