Abstract: A method includes generating a plurality of input vectors based on input signals to an electric circuit, selecting a subset of the plurality of input vectors, and determining a plurality of datapoints based on the selected subset of the plurality of input vectors. Each datapoint of the plurality of datapoints indicates a power consumption of the electric circuit corresponding to an input vector of the selected subset of the input vectors. The method also includes generating, by a processor, a plurality of vector sequences based on the selected subset of the plurality of input vectors. Each vector sequence of the plurality of vector sequences includes a portion of the selected subset of the plurality of input vectors arranged chronologically. The method further includes training a machine learning model based on a first subset of the plurality of vector sequences and a corresponding first subset of the plurality of datapoints.

Abstract: Systems and methods to dynamically adjust operating conditions of a graphics processing unit (GPU) are disclosed. A machine learning model is trained to determine operating voltages and frequencies to be provided to a GPU core of the GPU to execute a workload comprising a plurality of commands. The trained machine learning model is deployed to firmware of the GPU. A command in the workload to be executed by the GPU core is received. The trained machine learning model determines operating voltage and frequency for the GPU core to execute the command.

Abstract: An integrated circuit (IC) includes a debug controller, a debug state machine (DSM), and an extended performance monitor counter (EPMC). The debug controller that selectively outputs debug data on a debug interconnect. The DSM identifies an event based on the debug data and an event list and outputs a DSM indication that identifies the event. The EPMC indicates a plurality of detected events including the identified event. The EPMC indicates the identified event in response to the DSM indication.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs.

Abstract: A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

Abstract: In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying security vulnerabilities introduced by transformations to a hardware design. One of the methods includes obtaining a security model for an initial electronic hardware design and a modified electronic hardware design. An analysis process is performed on the initial representation and on the modified representation of the electronic hardware design according to the security model. If the modified electronic hardware design introduced a security vulnerability relative to the initial electronic hardware design, information representing the introduced security vulnerability is provided.

Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

Abstract: A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.

Abstract: A chip design method, a chip design device, a chip, and an electronic device are provided. The chip design method includes: determining at least one power state of the chip, one power state of the at least one power state including switch states of respective power domains on the chip in a chip operation mode, and the at least one power state including a first power state; determining control signals sent by changed power domains in the respective power domains in a case where a power state of the chip is switched to the first power state, in a case where the power state of the chip is switched to the first power state, switch states of the changed power domains changing; and analyzing timing dependency between the control signals to determine timing dependency between power domains to which the control signals act in the first power state.

Abstract: A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design. The first cone of influence corresponds to a first one or more inputs of the circuit design. The second cone of influence corresponds to a second one or more inputs of the circuit design. The method further includes determining a first shared circuit element of the circuit elements within a first intersection between the first cone of influence and the second cone of influence. Further, the method includes determining a first coupling factor based on the first intersection between the first cone of influence and the second cone of influence, and outputting the first shared circuit element and the first coupling factor to a memory.

Abstract: A method includes generating a plurality of vector sequences based on input signals of an electric circuit design and encoding the plurality of vector sequences. The method also includes clustering the plurality of encoded vector sequences into a plurality of clusters and selecting a set of encoded vector sequences from the plurality of clusters. The method further includes selecting a first set of vector sequences corresponding to the selected set of encoded vector sequences, selecting a second set of vector sequences from the plurality of vector sequences not in the first set of encoded vector sequences, and training, by a processing device, a machine learning model to predict power consumption using the first and second sets of vector sequences.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals.

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.

Abstract: Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

Abstract: A method for determining power output levels of a plurality of nodes in an electric power system includes receiving, at a first node of the plurality of nodes, voltage information and multipliers of all neighboring nodes of the first node within the electric power system, determining, by the first node, a local power generation and a local voltage using the voltage information and the multipliers of the neighboring nodes and distributing the local power generation and the local voltage to the neighboring nodes, determining, by the first node, an estimated voltage of each of the neighboring nodes and distributing the estimated voltage to each of the neighboring nodes, and updating, by the first node, a local multiplier using the voltage information received from the neighboring nodes and the estimated voltage of each of the neighboring nodes determined by the node.

Abstract: A method of testing a multiple power domain device includes sending a control signal from a test controller powered by a switchable power domain to a non-scan test data register powered by an always on power domain. The method further includes setting, using the control signal, a test data register value of the register to enable scan mode by bypassing an isolation cell between an output of the switchable domain and an input of the always on domain and, while the register value continuously enables scan mode: shifting a test pattern into a scan chain including a flip-flop coupled to the isolation cell, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result. The isolation cell is configured to allow or disallow propagation of a signal from the output to the input.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing timing behavior of an electronic design with a derived current waveform. A set of inputs is determined from a set of electrical characteristics of an electronic design or a portion thereof. Moreover, A derived current waveform is determined at one or more modules stored in memory and executing in conjunction with a microprocessor of a computing node based at least in part upon the set of inputs. The electronic design or the portion thereof is characterized based at least in part upon the derived current waveform.

Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.

Abstract: A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.

Abstract: A method and EDA software tool for analyzing and verifying that a multi-level power managed system description (IC design) is free of power-state combination conflicts by way of identifying and reconciling voltage level and power-state combination conflicts caused by reused blocks (IP cores). The reconciliation process involves generating Power-State Tables (PSTs) associated with each hierarchical circuit level (e.g., top/system level and lower/block levels) of the IC design using both initial power supply voltage values and reconciled/revised voltage values, which are determined by the main driver voltage levels of each power supply. Initial supply relationships generated using the initial PSTs are then compared with final supply relationships generated using the reconciled PSTs, whereby conflicts are identified when one or more initial supply relationship fails to match a final supply relationship, or when one or more final supply relationship fails to match an initial supply relationship.

Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.

Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.

Abstract: According to exemplary embodiments, a system and method for automated system power supply design is provided. The system and method enables circuit designers to quickly and independently design complicated single or multi rail power supply systems including multiple loads and sequencing requirements. The power solutions offered to designers may include all required power supplies to power up the loads including sequencers and load switches. The power supply design system may be implemented on a standalone processing unit, a distributed computing network, internet based web application, or among various other network applications.

Abstract: Example embodiments of disclosed configurations include a process (and system and non-transitory computer storage readable medium) for verifying an operation or a functionality of a design under test (DUT) through a distributed database processing system. In one or more embodiments, the emulator performs emulation of a DUT, and traces signals of the DUT based on the emulation. In one aspect, the traced signals are divided into multiple segments and are stored in the distributed database processing system in a form of key-value pairs. The distributed database processing system generates analysis segments based on corresponding segments of the traced signals and corresponding analysis rules. An analysis rule describes how to determine a particular characteristic of a corresponding segment of a signal. The distributed database processing system aggregates the analysis segments and generates a circuit analysis result indicating an aspect of the functionality of the DUT.

Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: Apparatus and methods for orienting power amplifiers are disclosed herein. In certain implementations, a method of determining the physical orientation of power amplifiers laid out on a printed circuit board (PCB) is provided. The method includes determining an amount of emissions radiated by a first power amplifier die that is positioned in a first orientation on the PCB. The method further includes determining an amount of emissions radiated by a second power amplifier die that is positioned in a second orientation on the PCB. The method further includes determining a third orientation of the second power amplifier die different than the second orientation, such that when the second power amplifier die is in the third orientation, the amount of emissions radiated by the first power amplifier die and the amount of emissions radiated by the second power amplifier die are distributed in different directions.

Abstract: A method and system for optimizing state assignments for a finite state machine. The method generates a random initial state assignment for each of a plurality of states of the finite state machine, determines an initial cost associated with the random initial state assignments, identifies a code swap to explore as a function of a code swap probability. Further, the method calculates a cost for the code swap when one or more criteria is satisfied, updates the code swap probability as a function of the cost of the code swap and a best cost, performs the code swap when the cost of the swap is smaller than the best cost and/or a current cost to optimize the state assignments, and outputs optimized state assignments.

Abstract: A method and system for optimizing state assignments for a finite state machine. The method generates a random initial state assignment for each of a plurality of states of the finite state machine, determines an initial cost associated with the random initial state assignments, identifies a code swap to explore as a function of a code swap probability. Further, the method calculates a cost for the code swap when one or more criteria is satisfied, updates the code swap probability as a function of the cost of the code swap and a best cost, performs the code swap when the cost of the swap is smaller than the best cost and/or a current cost to optimize the state assignments, and outputs optimized state assignments.

Abstract: A method for detecting a malfunction of a battery control system including a plurality of sensors intended to measure separate physical quantities of the battery, the method including the following steps: a) reading output values of the sensors; and b) determining, by means of a processing unit, whether the read values are consistent with a physical phenomenon conditioning relationships between at least two of the quantities.

Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.

Abstract: Vectorless dynamic power estimation for a circuit design may include forming, using a processor, a complex basic element within the circuit design, determining, using the processor, initial toggle rates for basic elements within the circuit design, and determining, using the processor, an initial toggle rate for the complex basic element. Vectorless dynamic power estimation further may include generating, using the processor, final toggle rates by updating the initial toggle rates according to a control signal analysis and calculating, using the processor, dynamic power dissipation for the circuit design using the final toggle rates.

Abstract: A heterogeneous power distribution system for an integrated circuit includes a power network-on-chip that receives electrical power from one or more off-chip power converters. The power network-on-chip includes a mesh of power routers to power a plurality of on-chip loads. The mesh of power routers includes a plurality of integrated simple routers and a plurality of integrated complex power routers. Each complex power router of the plurality of complex power routers includes a microcontroller which is communicatively coupled to one or more switches and one or more sensors of the complex power router. The microcontroller is configured to run a process algorithm that dynamically routes and controls power according to a power delivery policy by controlling the one or more switches based on information received from the one or more sensors. A method to determine a near optimal distribution of power supply resources in a heterogeneous power delivery system is also described.

Abstract: A chip layout can include a top-level portion and a set of blocks. The power-and-ground (PG) network for the chip layout can be specified by a set of chip-level PG constraints that is defined using a PG constraint definition language. The set of chip-level PG constraints can be characterized into new sets of PG constraints that correspond to smaller regions of the chip layout, e.g., a set of top-level PG constraints that corresponds to the top-level portion, and a set of block-level PG constraints for each block in the set of blocks. The new sets of PG constraints can then be provided to one or more instances of a PG compiler that executes on one or more processors to create the PG network for the chip layout.

Abstract: Technologies are generally described to provide a leakage current variability based power management of a processor. According to some examples, instruction counters and aggregated power consumption of the processor may be used to process power measurements of the processor into linear equations. The linear equations may be processed to produce a set of leakage values for the processor. In an example scenario, computation data from a power controller and processor instruction counters (PICs) of a core of the processor may be used to determine the leakage current variability of the core. A table of linear combination samples may be generated from the computation data. A micro-architectural leakage map of the core may be generated from the linear combination samples within the table.

Abstract: Formal verification of connectivity of a circuit, for example, a circuit representing a system on chip I/O ring is performed with low power considerations. The formal verification determines whether the connectivity of a circuit remains valid when low power design specification is introduced. The system receives assertions representing connectivity of the circuit. The system receives low power design specification for a circuit that describes power states of power domains of the circuit. The system generates combinational constraints representing valid power states of power domains of the circuit. The system performs formal verification based on the assertions representing the connectivity of the circuit and the combinational constraints representing the power states of power domains of the circuit. The result of the formal verification is used to determine whether the connectivity of the circuit is valid in view of the low power design specification.

Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.

Abstract: Example implementations described herein are directed to the generation of a specification for automatic power management of a network on chip and/or a system on chip. Such example implementations can include automatically generating a specification comprising at least one of a power domain, an always-on indicator, a voltage domain, a voltage level, and a clock frequency for each of one or more agents of a System on Chip (SoC) and a Network on Chip (NoC), the voltage domain indicative of power supply of the each agent, and the power domain indicative of one or more power switch rules applied to the each agent.

Abstract: An illumination apparatus for a vehicle is disclosed. The illumination apparatus comprises a trim portion affixed to a surface comprising a first photoluminescent portion and at least one light source. The light source may be configured to emit a first emission at a first wavelength. The first emission may be configured to excite the first photoluminescent portion in a back-lit configuration. The trim portion is configured to mask the first photoluminescent portion from external light sources to prevent excitation of the first photoluminescent portion in the presence of external light sources.

Abstract: Estimating power consumption of a circuit design includes associating, using a processor, each partition of a plurality of partitions of a circuit design with a probability distribution (315). For each partition, the associated probability distribution specifies a distribution for a probability distribution parameter correlated with power consumption for the partition. Using the processor, an output probability distribution specifying power consumption of the circuit design can be calculated according to the probability distribution of each partition of the circuit design (320).

Abstract: Aspects of the invention relate to techniques for estimating power and thermal profiles for an integrated circuit design. With various implementations of the invention, a group of devices is identified in a netlist based on information of the group of devices. The netlist may be a schematic netlist or a layout netlist extracted from a layout design. Power consumption information for the group of devices is determined based on device parameters for the group of devices and a lookup table. The determined power consumption information is then associated with layout location information. A thermal profile may then be estimated based on the power consumption information.

Abstract: Approaches for estimating power consumption of an electronic circuit from values of configuration parameters. A user is prompted for values of a first subset of the configuration parameters in a first user interface window that is separate from a second user interface window that provides default values of a second subset of the configuration parameters. An estimated level of power consumption of the electronic circuit is determined by a computer as a function of the user-entered values of the first subset of parameters and the default values of the second subset of parameters. The estimated level of power consumption, the user-entered values of the first subset of parameters, and the default values of the second subset of parameters are simultaneously displayed in a third user interface window. The values of both the first subset and second subset of parameters are editable in the third user interface window.

Abstract: A register transfer level (RTL) design is received which models a digital circuit in terms of the flow of digital signals. A power intent description is received which may include a description of power domains, identification of retention flops for each power domain, a list of isolation signals, and power switch definitions. A transformed RTL is produced accounting for functionality described in the power intent description. The transformed RTL includes flops designated as retention flops and non-retention flops. A retention flop module analyzes the flops to ensure that flops are properly designated as retention or non-retention flops. A verification module performs power aware sequential equivalence checking on various RTL and power intent descriptions to verify that RTL and power intent description outputs behave the same when accounting for power states.

Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

Abstract: A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

Abstract: One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.