Design Verification (functional Simulation, Model Checking) Patents (Class 716/106)
  • Patent number: 10318667
    Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention can update the coverage schema, wherein updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generate constraints used to satisfy requirements for meeting the first and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated schema.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Madhusudan Kadiyala, John Paul
  • Patent number: 10318691
    Abstract: Methods and systems for timing analysis and optimization of asynchronous circuit designs are disclosed. Registration stages are placed between combinational logic circuits. For timing purposes, the registration stages are modified to have a duplicate set of pins. New paths are formed in the circuit for the purposes of timing analysis. The paths are analyzable by timing tools. Once the timing analysis is complete, the paths are reverted to original paths, and new devices are selected for the circuit design based on results of the timing analysis. An updated design is sent for manufacture, based on the timing analysis and optimization of the asynchronous circuit.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Wave Computing, Inc.
    Inventors: Philippe Francis Sarrazin, Roger David Carpenter
  • Patent number: 10311185
    Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 4, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiung Liao, Min-Hsiu Tsai
  • Patent number: 10311187
    Abstract: A simulation method includes receiving a netlist describing a plurality of devices, performing an arithmetic operation by using values of random telegraph signal (RTS) noise factors respectively corresponding to the plurality of devices, generating an RTS model corresponding to each of the devices, based on a result of the arithmetic operation, and generating a netlist in which the RTS model is reflected.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Wook Jeon, Hyo-Eun Park, Keun-Ho Lee, Ui-Hui Kwon, Jong-Chol Kim
  • Patent number: 10305773
    Abstract: Systems and methods for device identity augmentation. In some embodiments, an Information Handling System (IHS) may include a processor and a memory coupled to the processor, the memory including program instructions stored thereon that, upon execution by the processor, cause the IHS to: receive high-level metrics; receive low-level metrics; determine, using a plurality of sets of threshold values, that the high-level metrics and the low-level metrics match at least one of a plurality of device profiles; and at least one of: (a) identify a device as belonging to class of devices corresponding to the matching device profile, or (b) identify whether at least a subset of the high-level metrics or the low-level metrics are outside one or more of the sets of threshold values.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 28, 2019
    Assignee: Dell Products, L.P.
    Inventors: Todd Erick Swierk, Marc Randall Hammons, Tyler Ryan Cox, Anantha K. Boyapalle
  • Patent number: 10295996
    Abstract: This test device for a monitoring control device includes an input/output controller, a logic controller, a logic connector, a logic executing simulator, a test target indication unit, an apparatus characteristic receiver, a logic managing simulator, and a logic connection information generator. Using an apparatus characteristic obtained by the apparatus characteristic receiver, the logic managing simulator specifies a simulation logic appropriate for a control logic on the basis of a simulation logic management rule. The logic connector connects the control logic and the simulation logic, by using logic connection information generated on the basis of a logic connection rule.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 21, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Keigo Yoshida, Mitsunobu Yoshinaga, Shinichiro Tsudaka
  • Patent number: 10285276
    Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 7, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Taranjit Kukal, Arnold Ginetti, Steven R. Durrill, Abhay Agarwal, Vikas Kohli, Tyler Lockman
  • Patent number: 10282833
    Abstract: Optical verification testing of an IC includes obtaining images of the IC by, for each image: (i) illuminating the IC with excitation light, wherein the excitation light corresponds to a respective specific optical excitation of a predefined spectrum of optical excitations (e.g., wavelength spectrum); and (ii) detecting scattered light from the IC in response to the specific optical excitation. For each of a set of sub-regions of the images, the respective sub-region is mapped to at least one of (i) a specific sub-unit of a predefined set of sub-units (e.g., gates) of the IC and (ii) a null result, thereby creating a representation of a detected layout of the IC as an arrangement of the sub-units. The representation can be used to verify that an as-fabricated layout is consistent with an as-designed layout, to detect unauthorized modifications of the IC structure.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 7, 2019
    Assignee: Trustees of Boston University
    Inventors: Ronen Adato, Ajay Joshi, M. Selim Unlu, Bennett B. Goldberg
  • Patent number: 10248754
    Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Uwe Paul Schroeder, Fadi Batarseh, Karthik Krishnamoorthy, Ahmed Omran
  • Patent number: 10223420
    Abstract: A node type of a plurality of distributed nodes to which a table to be added to a distributed database should be assigned can be identified by applying a set of placement rules defined for the table. The set of placement rules can also be applied to determine whether the table should be partitioned into more than one partition. A table group name associated with the table can be obtained and used in conjunction with the node type and determination of whether to partition the table to store the table in the distributed database on at least one node of the plurality of nodes as one or more partitions.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: March 5, 2019
    Assignee: SAP SE
    Inventors: Hans-Joerg Leu, Christian Bensberg, Johannes Beigel, Jochen Becker, Carsten Mueller
  • Patent number: 10216888
    Abstract: The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule check (“PERC”) rules and one or more constraints to the electronic design, wherein the one or more PERC rules are configured to perform one or more electrical rule checks.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: February 26, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mikhail Kanshin, Andrey Freidlin, Alexey Kalinov, Andrei Savelev, Douglas M. Den Dulk, Wojciech Wojciak
  • Patent number: 10180053
    Abstract: A method for determining a connectivity of at least one fracture to other fractures in an earth formation includes: obtaining connectivity information for each fracture of interest in the earth formation where the connectivity information for each fracture of interest includes connections with other fractures. The method further includes converting the connectivity information for each fracture of interest into a conjunctive normal form and determining the connectivity of the at least one fracture to other fractures by solving the connectivity information for each fracture of interest in the conjunctive normal form using a Boolean Satisfiability problem solver.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 15, 2019
    Assignee: BAKER HUGHES, A GE COMPANY, LLC
    Inventor: Tobias Hoeink
  • Patent number: 10162915
    Abstract: According to the present invention, a method and system for emulating multiple electronic designs on a single testbench is disclosed wherein number of instances of the original design to be connected on a single testbench is derived by calculating the capacity of the design and the testbench. It further creates a new wrapper design corresponding to number of instances of the original design; and selectively adapt the design for emulation.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 25, 2018
    Inventor: Prateek Sikka
  • Patent number: 10162920
    Abstract: The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include identifying at least one element reference upon which local name resolution was not performed and obtaining an appropriate element reference from the registry database. Embodiments may further include reviewing at least one secondary design unit for one or more local declarations and performing local name resolution for one or more remaining element references using a design hierarchy.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 25, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan Lee DeKock, Steven G. Esposito, Manu Chopra, Meir Ovadia
  • Patent number: 10133803
    Abstract: This application discloses a computing system implementing a source application to extract coverage data from a source database with application program interface (API) routines specific to the source database, and classify the coverage data according to a Unified Coverage Interoperability Standard (UCIS)-compliant format. The coverage data can include at least one of data from verification operations performed on a circuit design, test information utilized during the verification operations, or at least one test plan. The computing system implementing the source application can, based on the classification, select exchange routines to transfer the coverage data towards a target database. The computing system can implement a target application to utilize the classification of the coverage data to identify corresponding API routines specific to the target database, and write the coverage data to the target database with the identified API routines.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: November 20, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Darron May, Samiran Laha
  • Patent number: 10102324
    Abstract: A method for reuse of extracted layout-dependent effects for circuit design using circuit stencils includes receiving a schematic of an integrated circuit including a circuit segment. A circuit stencil corresponding to the circuit segment is instantiated in a schematic of a second integrated circuit. The circuit stencil includes layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit. Simulation is performed on the schematic of the second integrated circuit using the layout-dependent effects information for the circuit segment. A layout of at least a portion of the second integrated circuit corresponding to the circuit segment is generated responsive to performing the simulation.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: October 16, 2018
    Assignee: Synopsys, Inc.
    Inventors: Donald John Oriordan, Friedrich Gunter Kurt Sendig
  • Patent number: 10083303
    Abstract: An exemplary system, method and computer-accessible medium for detecting the presence of a Trojan(s) in a circuit(s), can include, for example, receiving information related to a property(s) configured to determine the presence of the Trojan(s), and determining the presence of the Trojan(s) based on the property(s) and a design(s) of the circuit(s) using a bounded model checking tool.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: September 25, 2018
    Assignee: New York University
    Inventors: Vivekananda Vedula, Jeyavijayan Rajendran, Arunshankar Dhandayuthapany, Ramesh Karri
  • Patent number: 10061879
    Abstract: An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits. The local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 28, 2018
    Assignee: Altera Corporation
    Inventor: Michael Hutton
  • Patent number: 10060978
    Abstract: A method and circuits are provided for implementing enhanced scan data testing using an XOR network to prioritize faults to be simulated during diagnostic isolation, and reducing the number of faults requiring re-simulation. A test is run, scan data are applied to scan channels using the XOR network and the output scan data are unloaded. A list of possible faults is identified based on pin flips, and the possible faults to be simulated during diagnostic isolation are prioritized by a number of occurrences in the list, and possible faults are further graded to reduce the number of possible faults requiring re-simulation.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 10055513
    Abstract: A development device for configuring a model of a technical system to represent signal paths, in particular on a computer with a display, wherein the model depicts at least two signal paths of the technical system and, in an initial representation, all input signals, output signals, and all processing units are depicted in the form of block elements in a circuit diagram, characterized in that the development device is configured to reduce the representation of the model to the signal path of the selected signal once any desired input signal or output signal has been selected, wherein only the relevant processing units are displayed or highlighted.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: August 21, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Egon Krenzer
  • Patent number: 10049173
    Abstract: Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 14, 2018
    Assignee: Synopsys, Inc.
    Inventors: Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma
  • Patent number: 10037396
    Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: July 31, 2018
    Assignee: Altera Corporation
    Inventors: Ryan Fung, David Lewis, Valavan Manohararajah
  • Patent number: 10031990
    Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. The method may include receiving, using a processor, an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. The method may further include identifying a plurality of X sources associated with the verification environment and modifying the plurality of X sources based upon, at least in part, the symbolic constant. The method may also include running a first target node and if the first target node is proven, run at least one additional target node until all target nodes are proven.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 24, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pradeep Goyal, Deepak Yadav, Jasmeet Singh Narula
  • Patent number: 10025896
    Abstract: A computerized method of creating a circuit logic model of a VLSI device, comprising mapping a plurality of logic function patterns of one or more circuits of a VLSI device through a plurality of probe iterations and generating a circuit logic model of the circuit(s) by reconstructing a logical function of a combinatorial logic of the circuit(s) based on analysis of the logic function patterns. Each of the probe iteration comprises switching between scan shift mode and functional mode of the VLSI device such that while the VLSI device operates in scan shift mode register(s) associated with the circuit(s) is accessed and while the VLSI device operates in functional mode external pin(s) of the VLSI device associated with the circuit(s) is probed and mapping a respective one of the logic function patterns according to a logic state of one or more bits in the register(s) and/or the external pin(s).
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: July 17, 2018
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Leonid Azriel, Abraham Mendelson, Ran Ginosar
  • Patent number: 10013375
    Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Jin Kim, Nak-Hee Seong, Hee-Seong Lee
  • Patent number: 9977845
    Abstract: A method of performing a static timing analysis on an integrated circuit includes loading a library that includes local random variation information of the integrated circuit and global variation information of the integrated circuit that is obtained based on a set of a plurality of global variation parameters of the integrated circuit, calculating delays of timing arcs included in the integrated circuit based on the library, and determining whether at least one timing path of a plurality of timing paths included in the integrated circuit violates a timing constraint based on the delays of the timing arcs in the at least one timing path, the local random variation information of the integrated circuit and the global variation information of the integrated circuit.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Moon-Su Kim
  • Patent number: 9965580
    Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 8, 2018
    Assignee: NTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Fei Gou, Bodo Hoppe, Yang Li, Dan Liu, Yang Liu
  • Patent number: 9933486
    Abstract: A test pattern generation apparatus includes an input unit, an output unit, and a pattern generating unit configured to, when a source code based on a system description language is created through the input unit, store an execution file created from the source code, generate a test pattern from the execution file according to an external command for testing a semiconductor apparatus as a DUT, and output the generated test pattern through the output unit.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 3, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Patent number: 9934354
    Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 3, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Balvinder Singh, Steven R. Durrill, Arnold Ginetti, Vikrant Khanna, Abhishek Dabral, Madhur Sharma, Nikhil Gupta, Ritabrata Bhattacharya
  • Patent number: 9928336
    Abstract: Disclosed are techniques for simplifying an electronic design for verification by domain reduction. These techniques extract one or more data flows for at least a portion of an electronic design under verification, construct a comparison graph comprising tokens and edges for the at least the portion of the electronic design, color the comparison graph with a number of colors, and reduce a domain size of the at least the portion of the electronic design based in part or in whole upon the number of colors.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: March 27, 2018
    Assignee: Cadence Desisgn Systems, Inc.
    Inventor: Jun Yuan
  • Patent number: 9928317
    Abstract: Techniques for employing an additive design process to design heat sinks are disclosed. A heat sink “grows” through an iteration process. During each iteration step, an object is added to a location determined based on simulation. The criterion for the determination may be being a location having a highest fluid apparent surface temperature value or being a location having a highest bottleneck heat transfer characteristic value. The thermal performance of the newly derived structure is simulated. If a predetermined condition is met, the object is kept. Otherwise, the object is removed and the location is marked so that the same addition may not occur subsequently. The iteration process may be repeated.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: March 27, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Robin Bornoff, John Parry
  • Patent number: 9916234
    Abstract: Methods and systems for performing mainframe batch testing and/or property-based validation testing using a finite-state machine are provided. According to certain aspects, a validation server may receive a set of batch data designed to validate a property under test, such as during mainframe batch testing. A validation server may validate that the set of batch data is in a proper format. The validation server may then cause a finite-state machine to process instructions contained within the set of batch data. Once the finite-state machine processes the set of batch data, the validation server may then validate that the finite-state machine adheres to the property under test. If the validation fails, the validation server may generate an error report describing the failure.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: March 13, 2018
    Assignee: STATE FARM MUTUAL AUTOMOBILE INSURANCE COMPANY
    Inventors: Joseph W. Norton, James D. Titlow, Matthew W. Holloway, Amanda J. Tolonen, Venkata R. Kongara, Timothy J. Wheeler
  • Patent number: 9910941
    Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention includes updating the coverage schema, wherein the updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generating constraints used to satisfy requirements for meeting the first set of events and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated coverage schema.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Madhusudan Kadiyala, John Paul
  • Patent number: 9904759
    Abstract: A system for concurrent target diagnostics is disclosed. The system comprises dedicated FPGA for generating test data to test target connections between an emulator and a target system. In this way, domains of the emulator may continue to emulate at least a portion of a hardware design during the testing of the target connections. Further, a multiplexer operable to select target connections for testing eliminates errors resulting from manual swapping of target connections during the testing process. The system further comprises multiple paths to a target pod. The paths enable monitoring and reporting on the status of target connections between an emulator and a target system.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 27, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sundar Rajan, Charles R. Berghorn, Mitchell G. Poplack
  • Patent number: 9898379
    Abstract: A method for measuring the effect of microscopic hardware faults in high-complexity applications includes carrying out on a processing system a step of simulation of an electronic system that executes a software instance of the application. The simulation step includes injecting faults at a microscopic level and measuring a corresponding final effect. The operation of injecting faults includes selecting a microscopic fault to be injected, selecting a mutant corresponding to the microscopic fault, applying the selected mutant to the software instance to obtain a mutated instance, simulating the electronic system that executes the mutated instance, and measuring the corresponding effect.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventor: Riccardo Mariani
  • Patent number: 9858378
    Abstract: A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Shu-Yu Chen, Yu-Ti Su
  • Patent number: 9823305
    Abstract: A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 21, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Meir Ovadia, Swaminathan Venkateasan
  • Patent number: 9817939
    Abstract: Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more emulator FPGAs, the host system places debugging logic units of the debugging logic evenly across the FPGA before placing logic components of the DUT.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 14, 2017
    Assignee: Synopsys, Inc.
    Inventor: Ludovic Marc Larzul
  • Patent number: 9811617
    Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a regression. The computing system can define coverage for system level functionality of a circuit design as a set of system level coverage points. Each of the system level coverage points can correspond to a different portion of system level functionality of the circuit design. The computing system can correlate the system level coverage points in the set according to characteristics of the different portions of the system level functionality corresponding to the system level coverage points. The computing system can utilize the correlated set of system level coverage points to identify system level functionality left uncovered by events performed by the circuit design during simulation with one or more regressions.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: November 7, 2017
    Assignee: Mentor Graphics Corporation
    Inventor: Andreas Meyer
  • Patent number: 9792161
    Abstract: Disclosed systems and methods incorporate a sound and maximal causal model with control flow information for maximum concurrency error detection in general multithreaded programs. The maximal causal model may be based on or integrated with the sequential consistency model, and form the basis for a formula including branch and order variables as first-order logical constraints solvable by an SMT solver for detection or prediction of concurrency errors. The disclosed systems and methods also relate to predictive trace analysis (PTA) for predicting generic concurrency properties using local traces (as opposed to a global trace) through the threads of a multithreaded program. By uniformly modeling violations of concurrency properties and the thread causality as constraints over events, and using an SMT solver, the systems and methods predict property violations allowed by the causal model.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: October 17, 2017
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Jeff Huang, Grigore Rosu
  • Patent number: 9772917
    Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: September 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-hoon Jeong, Ho-young Kim, Soo-jung Ryu
  • Patent number: 9753086
    Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop os configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Young Kim, Sung-Wee Cho, Dal-Hee Lee, Jae-Ha Lee
  • Patent number: 9741823
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 22, 2017
    Assignee: Internation Business Machines Corporation
    Inventors: Andrew M. Greene, Balasubramanian S. Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre
  • Patent number: 9734263
    Abstract: Described is a method and apparatus for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing an architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit, recognizing method calls associated with the architectural verification environment, and generating a list of recognized method calls that is loaded for a debug program to debug the HDL architecture of the integrated circuit.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Erez Kohavi, Evgeniy Ainbinder
  • Patent number: 9702934
    Abstract: Systems and methods disclosed herein provide for efficiently loading mask data to the mask register bits from the decompression network outputs of an ATPG system. The systems and methods also provide an elastic interface utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the number of input variables utilized during the loading of the mask data to the mask register bits.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 11, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Dale Edward Meehl, Vivek Chickermane
  • Patent number: 9684527
    Abstract: An integrated computing system configuration system includes a computing system that executes an engine to receive component specifications for each of one or more components supplied by a plurality of suppliers, and receive user input for selecting a subset of the component specifications to be implemented in a customized integrated computing system by generating a base configuration that comprises the component specifications of the subset of the components. From the received component specifications and user input, the engine may generate a component classification for each component specification according to its functionality, validate each component classification according to one or more other component specifications in the subset of components, and display the validated components for each component on a display.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: June 20, 2017
    Assignee: VCE IP Holding Company LLC
    Inventor: Jeffery J. Hayward
  • Patent number: 9686733
    Abstract: A communication method in a wireless network is provided.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 20, 2017
    Assignee: THALES
    Inventors: Michel Delattre, Guy Bouyssounouse
  • Patent number: 9679101
    Abstract: A method, executed by a computer, for placing circuit elements includes determining an initial placement for a set of circuit elements corresponding to a circuit design, identifying a port for a circuit element of the set of circuit elements to provide an identified port, calculating a load-to-driver capacitance ratio for the identified port, determining an estimated operating parameter corresponding to the identified port if the load-to-driver capacitance ratio exceeds a selected threshold, and changing placement of the circuit element, or an associated driver, if the estimated operating parameter is outside an acceptable operating range. Changing placement of the circuit element or an associated driver can improve the estimated operating parameter corresponding to the identified port. In some embodiments, the estimated operating parameter is an estimated operating temperature.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Harald D. Folberth, Dilip A. Kumar, Sven Peyer, Sourav Saha, Hameedbasha Shaik
  • Patent number: 9679098
    Abstract: This application discloses a computing system to provide test stimulus to an electronic device modeled in a verification environment by the computing system. The computing system can identify transactions performed by the electronic device in the verification environment based, at least in part, on messages exchanged over an interconnect in the electronic device in response to the test stimulus. The computing system can output the transactions from the verification environment and bundle a plurality of the transactions based, at least in part, on messaging relationships defined by a communication protocol for the interconnect. The computing system can utilize the bundles of transactions to determine whether the electronic device functions in accordance with the communication protocol.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 13, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Andreas Meyer, Adam Erickson, Michael Concannon, Robert Fredieu
  • Patent number: 9672065
    Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.
    Type: Grant
    Filed: July 26, 2015
    Date of Patent: June 6, 2017
    Assignee: Rocketick Technologies LTD
    Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher