Logic Design Processing Patents (Class 716/101)
  • Patent number: 10289577
    Abstract: An exemplary system for wrapping an intellectual property core (IP) bus master(s), can include, for example, a plurality of IP cores associated with the IP core bus master(s), and a wrapper module connected to a serial input of the IP core bus master(s) and a serial output of the IP core bus master(s), where the wrapper module can be configured to capture and shift a plurality of values of a system bus for a plurality of bus transfers associated with the IP core bus master(s) and the IP cores. The wrapper module can be further configured to modify a wrapper control logic and a wrapper boundary register of the IP core bus master(s). A plurality of terminals can be included, which can be coupled to the IP core bus master(s), and a plurality of wrapper cells can be included, which can be associated with the plurality of terminals.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 14, 2019
    Assignee: New York University
    Inventors: Ramesh Karri, Jerry Backer, David Hely
  • Patent number: 10223491
    Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Joachim Keinert, Sridhar H. Rangarajan, Haoxing Ren, Sourav Saha
  • Patent number: 10223488
    Abstract: A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 5, 2019
    Assignee: Altera Corporation
    Inventor: Sergey Gribok
  • Patent number: 10203718
    Abstract: Generating delays for a clock circuit includes, determining, using a processor, groups of contexts for exit points of the clock circuit based upon a plurality of characteristics and a type selected from a plurality of different types for each characteristic, forming, using the processor, sub-groups of the exit points based upon delay values for the exit points, and determining, using the processor, a mean delay value for each sub-group.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 12, 2019
    Assignee: XILINX, INC.
    Inventor: Usha Narasimha
  • Patent number: 10176283
    Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 8, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Vijay Akkaraju, Chun Chan, Che-Hua Shih, Chia-Chih Yen
  • Patent number: 10169217
    Abstract: A computer-implemented system for generating test cases and/or test procedures to verify software having a nonlinear arithmetic constraint over a Real number range. The system includes a translator that receives, as input, software specification models for the software to be verified. The translator is configured to generate, as output, a plurality of SMT formulas that are semantically equivalent to the software specification models. The system includes an analytical engine pool that receives, as input, the plurality of SMT formulas from the translator and analyzes the plurality of SMT formulas, and generates, as output, test case data for each of the plurality of SMT formulas determined to be satisfiable. The system includes a post-processor that receives, as input, the test case data from the analytical engine pool and generates, as output, the test cases and/or test procedures for the software to be verified based on the test case data.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: January 1, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Han Yu, Michael Richard Durling, Kit Yan Siu, Meng Li, Baoluo Meng, Scott Alan Stacey, Daniel Edward Russell, Gregory Reed Sykes
  • Patent number: 10153769
    Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 11, 2018
    Assignee: New York University
    Inventors: Ozgur Sinanoglu, Youngok Pino, Jeyavijayan Rajendran, Ramesh Karri
  • Patent number: 10089431
    Abstract: A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 2, 2018
    Assignee: Arch Systems Inc.
    Inventors: Timothy Matthew Burke, Christopher Ling
  • Patent number: 10073974
    Abstract: A method includes analyzing a given application to determine one or more packages utilized by the given application, the one or more packages comprising a plurality of libraries, identifying a subset of the plurality of libraries utilized by the given application, determining one or more dependent libraries for each of the identified libraries in the subset, generating a given container for the given application, the given container comprising the identified libraries in the subset and the dependent libraries for each of the identified libraries, performing risk analysis for the given container including comparing a risk value calculated for the given container to a designated risk threshold, simulating one or more actions in the given container responsive to the risk value calculated for the given container exceeding the designated risk threshold, and determining whether to accept or reject the given container responsive to the risk analysis and simulated actions.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jinho Hwang, Clifford A. Pickover, Maja Vukovic
  • Patent number: 10048939
    Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 14, 2018
    Assignee: STC.UNM
    Inventor: James Plusquellic
  • Patent number: 9881842
    Abstract: A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical fins. A work function metal (WFM) layer is disposed on the dielectric layer. A first sidewall spacer and a second sidewall space are formed proximate to the first vertical fin and the second vertical fin, respectively. A lithographic mask is applied to a first area proximate to the first vertical fin including the first vertical fin, and a portion of the WFM layer proximate to the first vertical fin. A portion of the WFM layer proximate to the second sidewall spacer is recessed below an upper surface of the second sidewall spacer. The lithographic mask is removed. A portion of the dielectric layer is removed to produce a wimpy vertical transport device and a nominal vertical transport device on the substrate structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Su Chen Fan, Catherine B. Labelle, Xin Miao
  • Patent number: 9836567
    Abstract: A method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Asher Berkovitz, Uzi Magini, Michael Priel
  • Patent number: 9760532
    Abstract: Solving a multidimensional multicriteria optimization problem is difficult because the correlations and dependencies between solutions, target functions, and variation variables can be detected only with difficulty. In order to facilitate this, it is proposed that a model space (1) and a variation space (2) are displayed simultaneously and in an interactively linked fashion.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: September 12, 2017
    Assignee: AVL List GmbH
    Inventors: Klemens Wallner, Alejandra Garcia, Adnand Dragoti
  • Patent number: 9715564
    Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Ashutosh Misra, Pradeep K. Nalla
  • Patent number: 9654109
    Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 16, 2017
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Jeffrey T. Watt
  • Patent number: 9594860
    Abstract: An approach is provided in which a hybrid mixed signal equivalence checking system partitions a mixed signal reference model and a mixed signal model under verification into analog sections and digital sections. The hybrid mixed signal equivalence checking system simulates the analog sections from the two different models to determine analog equivalence. As such, the hybrid mixed signal equivalence checking system verifies digital equivalence between the digital reference section and the digital section model under verification in response to evaluating one or more difference functions that represent at least a portion of the first digital section and the second digital section. As a result, the hybrid mixed signal equivalence checking system verifies equivalence between the mixed signal reference model and the mixed signal model under verification based upon the verified analog equivalence and the verified digital equivalence.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Himyanshu Anand, Magdy S. Abadir
  • Patent number: 9536029
    Abstract: For linear array hierarchy navigation, a method encodes a logic design as a linear array with a plurality of logic states. The method displays combination maps of a plurality of fields at two or more successive display levels having a top display level and at least one lower display level. In addition, the method receives a selection of a first field of the plurality of fields. The method displays the first field and one or more successive combination maps for the first field. Each of the one or more successive combination maps is displayed with a field identifier of a predecessor field. In addition, the method displays relationship arrows linking the first field and each successive field of the first field.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 3, 2017
    Assignee: Assurant Design Automation LLC
    Inventor: M. David McFarland
  • Patent number: 9424389
    Abstract: A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anthony G. Aipperspach, Derick G. Behrends, Todd A. Christensen, Jesse D. Smith
  • Patent number: 9038008
    Abstract: A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 19, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Jaideep Mukherjee, Richard J. O'Donovan
  • Patent number: 9030231
    Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventors: David Lewis, Valavan Manohararajah, David Galloway
  • Patent number: 9032346
    Abstract: Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: May 12, 2015
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Raymond A. Filippi, Paul Soh, Hui May Tan
  • Patent number: 9032350
    Abstract: A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x?1 switch circuits to connect x?1 data circuits to through silicon vias 1 to x?1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
  • Patent number: 9026961
    Abstract: Techniques for performing race logic synthesis on an integrated circuit (IC) are described herein. According to one aspect of the invention, ESL (electronic system level) and any HDL (hardware description language) design source files of an IC design are compiled into a design database. Race logic analysis is performed on the IC design to detect race logic, including race logic for IPC (inter-process communication) and IPS (inter-process synchronization) objects in the IC design, by a third-party tool and/or by the same host EDA (electronic design automation) tool that will be performing race logic synthesis on the IC design, if the latter has built-in race logic audit functions. Based on the race logic audit results, race logic synthesis is performed on the design database, and getting rid of all identified race logic in the IC design, including IPC- and IPS-related race logic.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 5, 2015
    Inventor: Terence Wai-Kwok Chan
  • Patent number: 9026960
    Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 5, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chayan Majumder, Pawan Fangaria
  • Patent number: 9026962
    Abstract: An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and have manufactured a specific class of custom electronic device, namely a computer processing unit with embedded software. A Graphical User Interface (GUI) is provided as the front-end to a Computer Aided Design (CAD) server that generates sophisticated control and manufacturing instructions that are delivered to a fabrication supply chain, which produces a specified device that is then transported via managed logistics into inventory and ordering systems at vendors for delivery to a designated customer.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: May 5, 2015
    Assignee: Gumstix, Inc.
    Inventors: Walter Gordon Kruberg, Neil C. MacMunn
  • Publication number: 20150121319
    Abstract: A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: Altera Corporation
    Inventors: Michael D. Hutton, Chuck Rumbolt, Jeffrey Fox, Herman Henry Schmidt
  • Patent number: 8990741
    Abstract: A processing part inputs a behavior description code in which a write access array to be accessed to write and a read access array to be accessed to read are used. The processing part analyzes the behavior description code, and determines an order of using each write access address and an order of using each read access address when the behavior description code is executed. Further, the processing part performs either one of a write access order changing process to change the order of using the write access addresses when the behavior description code is executed based on the order of using the read access addresses and a read access order changing process to change the order of using the read access addresses when the behavior description code is executed based on the order of using the write access addresses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: March 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Ryo Yamamoto
  • Patent number: 8977993
    Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Synopsys, Inc.
    Inventors: Qian-Ying Tang, Qiang Chen, Sridhar Tirumala
  • Patent number: 8977997
    Abstract: Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Mentor Graphics Corp.
    Inventors: Arthur Jesse Stamness, Brian Etscheid, Randy Misustin
  • Patent number: 8977992
    Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Innovative Memory Systems, Inc.
    Inventor: Raul-Adrian Cernea
  • Patent number: 8977996
    Abstract: A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a cluster generation task (302) which generates clusters based on the parse tree, each of the clusters including a group of source codes which can operate independently, a log file task (303) which generates a log file based on a structure of the cluster, and a comparison task (304) which compares a first log file of a previous cluster with a second log file of a current cluster and re-uses previous exploration result based on a comparison result, the first log file being obtained from a previous design space exploration, the second log file being generated from a current operation.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: March 10, 2015
    Assignee: NEC Corporation
    Inventor: Benjamin Carrion Schafer
  • Patent number: 8977999
    Abstract: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: March 10, 2015
    Assignee: Synopsys, Inc.
    Inventors: Mahesh A. Iyer, Amir H. Mottaez
  • Patent number: 8966413
    Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 24, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ofer Shacham, Mark Horowitz, Stephen Richardson
  • Patent number: 8959469
    Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Altera Corporation
    Inventors: Doris Tzu-Lang Chen, Deshanand Singh
  • Patent number: 8954902
    Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: February 10, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Mark L. Burgener, Alexander Dribinsky, Tae Youn Kim
  • Patent number: 8954908
    Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: February 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Jushan Xie, Michael Tian, An-Chang Deng
  • Patent number: 8954905
    Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: February 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hurley Song, Denis Baylor, Matthew Robert Rardon
  • Patent number: 8949751
    Abstract: A method for visually verifying an implementation of a design is described. The method includes integrating logical design data, physical design data, and physical implementation data into a common data format and graphically displaying the commonly formatted data to provide a visualization of the design, the visualization including a spatial context component associated with the physical implementation data.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: February 3, 2015
    Assignee: The Boeing Company
    Inventors: Brent Hadley, Patrick Jan Eames, Michael Patrick Sciarra, Charles Mark Williams
  • Patent number: 8949767
    Abstract: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 3, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Jeanne P. Bickford, John R. Goss, Nazmul Habib, Robert McMahon
  • Patent number: 8949759
    Abstract: In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 8943448
    Abstract: A hardware model database is identified which stores a graph-based common representation of a hardware design that includes hardware module nodes each representative of a unique module of the hardware design and associated with one or more instances of the unique module. Additionally, a signal dump resulting from a simulation of a logic code model of the hardware design is identified. Each instance of each unique module is identified using the hardware model database, and for each assertion condition included therein, a corresponding value for the assertion condition is determined from the signal dump. Further, a construct of the hardware design corresponding to each instance of each unique module is conditionally displayed by a debugger application, based on the determined values of the corresponding assertion conditions included in the instance of the unique module.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventor: Robert Anthony Alfieri
  • Patent number: 8918752
    Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Oracle International Corporation
    Inventors: Alex Chow, Robert J. Drost, Ronald Ho, Robert D. Hopkins, Ivan E. Sutherland
  • Patent number: 8914756
    Abstract: The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA2) corresponding to the analog block is produced in a native technology and a second integrated-circuit portion (BN2) corresponding to said digital block, is produced in a shrunk technological version associated with said native technology.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: December 16, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Guilhem Bouton
  • Patent number: 8912625
    Abstract: Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Patent number: 8910100
    Abstract: The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected devices within a graphical representation of a circuit design such as a circuit layout, circuit mask, or a schematic. The system and method provide for discerning the intended insertion points and performing remedial transformations of the devices within the chains to ensure compliance with both structural and operational requirements of the circuit design.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: December 9, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thomas Wilson, Arnold Ginetti, Kenneth Ferguson, Yuan-Kai Pei
  • Patent number: 8904322
    Abstract: An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vikas Agarwal, Samantak Gangopadhyay, Shashank Joshi, Manish Kumar
  • Patent number: 8896344
    Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: November 25, 2014
    Assignee: Altera Corporation
    Inventors: David Lewis, Valavan Manohararajah, David Galloway
  • Patent number: 8898618
    Abstract: The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a schematic diagram and greatly eases the process of traversing, debugging, and analyzing the schematic diagram. Users can choose to dynamically group the circuit elements on the schematic diagram without going through any compilation or synthesis process. Users can also choose to revert any of the entities back to the original schematic diagram with the ungrouping operation. For specific or batch manipulation of the schematic diagram, the tool provides a scripting interface for users to enter commands.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: November 25, 2014
    Assignee: Altera Corporation
    Inventors: Choi Phaik Chin, Denis Chuan Hu Goh
  • Patent number: 8890567
    Abstract: In one aspect, a method of testing an IC is provided. In one embodiment, the method includes: programming a resistive element in the IC at an intermediate ON state, where in addition to the intermediate ON state, the resistive element has another ON state, further where at the intermediate ON state, the resistive element has a resistance that is at least 10 times greater than a resistance of the resistive element at the another ON state; and applying test data to the resistive element.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 18, 2014
    Assignee: Altera Corporation
    Inventor: David Lewis
  • Publication number: 20140337811
    Abstract: A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow.
    Type: Application
    Filed: April 16, 2014
    Publication date: November 13, 2014
    Applicant: Synopsys, Inc.
    Inventor: Kevin Knapp