Abstract: A processing device comprises a first set of processors comprising a first processor and a second processor, each of which comprises at least one controllable port, a first memory operably coupled to the first set of processors, at least one forward data line configured for one-way transmission of data in a forward direction between the first set of processors, and at least one backward data line configured for one-way transmission of data in a backward direction between the first set of processors. wherein the first set of processors are operably coupled in series via the at least one forward data line and the at least one backward data line.

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

Abstract: Techniques facilitating cached result use through quantum gate rewrite are provided. In one example, a computer-implemented method comprises converting, by a device operatively coupled to a processor, an input quantum circuit to a normalized form, resulting in a normalized quantum circuit; detecting, by the device, a match between the normalized quantum circuit and a cached quantum circuit among a set of cached quantum circuits; and providing, by the device, a cached run result of the cached quantum circuit based on the detecting.

Abstract: In some embodiments, a computing system may comprise a memory for storing a ledger; a computer processor for verification of the ledger, wherein the computer processor comprises at least one of a classical computer processor configured to run a virtual quantum machine and a quantum computer comprising a plurality of qubits; wherein the ledger is configured to store arbitrary classical information and quantum information which is verifiable using the computer processor. Furthermore, in some embodiments the computing system is configured to perform operations comprising: adding to the ledger using the computer processor to solve a mathematically difficult problem which is Quantum-Merlin-Arthur-complete (QMA-complete). In embodiments, a blockchain includes a quantum state. In some aspects, a unitary operator corresponding to a quantum rotation is found when new transaction data are to be secured in the blockchain.

Abstract: Simulation of a circuit design using accelerated models can include determining, using computer hardware, that a design unit of a circuit design specified in a hardware description language is a prime block and determining, using the computer hardware, an output vector corresponding to an output of the prime block. Using the computer hardware, contents of the prime block can be replaced with an accelerated simulation model specified in a high level language, wherein the accelerated simulation model can determine a value for the output of the prime block as a function of values of one or more inputs of the prime block using the output vector. Using the computer hardware, the circuit design can be elaborated and compiled into object code that is executable to simulate the circuit design.

Abstract: Techniques that combine quantum error correction and quantum error mitigation are used to simulate a fault-tolerant T-gate with low sampling overhead using the quasiprobability decomposition method. In some embodiments, the T-gate can be simulated using two logical bits and a magic state preparation that mitigates the need for magic state distillation and consequently has a low sampling overhead. Alternatively, the T-gate can be simulated based on code deformation performed on the surface code. Noise is removed from the T-gate using quasiprobability decomposition based on a learned logical error rate.

Abstract: A computer implemented method includes receiving a digital description of a quantum circuit, partitioning the digital description of the quantum circuit into a plurality of quantum sub-circuits wherein each quantum sub-circuit of the plurality of quantum sub-circuits comprises one or more quantum gates, determining sub-circuit dependencies for the plurality of quantum sub-circuits, simulating the plurality of quantum sub-circuits according to the sub-circuit dependencies to produce simulation results for each quantum sub-circuit of the plurality of quantum sub-circuits, wherein a first and a second quantum sub-circuit of the plurality of quantum sub-circuits each contain one or more gates that are applied to a common qubit, and wherein the first and the second quantum sub-circuit are simulated independently using an entangled tensor index. A corresponding computer system and computer program product are also disclosed herein.

Abstract: One embodiment can provide a system for determining a hybrid-manufacturing process plan for manufacturing a printed circuit board (PCB). During operation, the system can obtain a set of hybrid-manufacturing constraints. The set of hybrid-manufacturing constraints can include a set of primitives, a set of atoms, and an atom end-state vector. A primitive can represent an additive or a subtractive manufacturing process corresponding to one or more atoms of the PCB. An atom can correspond to a unit of spatial volume of the PCB. The system can determine a plurality of feasible hybrid-manufacturing plans based on the set of hybrid-manufacturing constraints. Each feasible hybrid-manufacturing plan can represent an ordering of the set of primitives satisfying the atom end-state vector. The system can determine costs for manufacturing the PCB using the plurality of feasible hybrid-manufacturing plans. The system can determine, based on the costs, an optimized hybrid-manufacturing plan for manufacturing the PCB.

Abstract: A method for design optimization of a quantum circuit includes analyzing a first quantum circuit design based on at least one of a set of design criteria, wherein the first quantum circuit design includes a set of quantum logic gates, and wherein a design criterion in the set of design criteria includes changing a size of a matrix of transformations corresponding to a number of qubits employed in the first quantum circuit design. The embodiment further includes in the method modifying the first quantum circuit design into a transformed quantum circuit design, the modifying causing the transformed quantum circuit design to perform an operation implemented in the first quantum circuit design with a changed matrix of transformations.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.

Abstract: A method for generating redundant configuration in FPGA devices includes: analysing the configuration pertaining to a given design to be configured, or already configured, in the FPGA device, in order to identify programmed and empty configuration memory portions, configuring the FPGA device for implementing said design, measuring the power consumption of the configured FPGA device, copying the configuration from at least some subsets of the programmed portion to subsets of the empty portion, (a) verifying the configuration read back from said subsets of the empty portion with the configuration data read from said subsets of the programmed portion, (b) verifying whether the functionality of the design after the copy is still correct, (c) measuring the power consumption of the FPGA device, and verifying whether the power consumption of the FPGA device after the copy is acceptable according to pre-defined criteria, if the verification steps (a), (b) and (c) are all successful the redundant configuration is corr

Abstract: Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.

Abstract: Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.

Abstract: Disclosed herein is a method of generating an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which a high-level synthesis unit generates a control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.

Abstract: A method and system for analysis of an electronic facility may include providing a mathematical analysis using a scoring system to make generalization about a design and select locations for placement of trojans, triggers and trojan detection instruments within an electronic facility. Such mathematical analysis may include Controllability-Observability analysis as applied to trojan insertion and attacks, and trojan detection instruments.

Abstract: Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.

Abstract: Techniques facilitating cached result use through quantum gate rewrite are provided. In one example, a computer-implemented method comprises converting, by a device operatively coupled to a processor, an input quantum circuit to a normalized form, resulting in a normalized quantum circuit; detecting, by the device, a match between the normalized quantum circuit and a cached quantum circuit among a set of cached quantum circuits; and providing, by the device, a cached run result of the cached quantum circuit based on the detecting.

Abstract: Disclosed approaches for pipelining signal paths in an integrated circuit (IC) device include receiving by a design tool a circuit design to be implemented in the integrated circuit device. The design tool identifies signals of the circuit design that require pipeline registers between drivers and loads of the signals, and relaxes an initial timing requirement to a relaxed timing requirement. The design tool determines respective numbers of pipeline registers to insert between each driver and load of each of the signals based on the relaxed timing requirement. The design tool inserts in the circuit design, respective sets of the respective numbers of pipeline registers between each driver and load of each of the signals. The design tool places the respective sets of the pipeline registers on the IC device using the initial timing requirement.

Abstract: The present disclosure describes a method for replacing a device with a cell structure having a plurality of uni-gates. An exemplary method includes receiving a circuit diagram that includes the device, determining the cell structure wherein a cumulative effective gate length of the plurality of uni-gates is equal to a gate length of the device, generating, based on the cell structure and the device, a floor plan that includes an arrangement of a plurality of placeholders that match an arrangement of the cell structure and an arrangement of the device in the circuit diagram, and generating a circuit layout based on the floor plan, the cell structure, and the circuit diagram. The plurality of placeholders is replaced by the cell structure and the cell structure is connectable to other parts of the circuit diagram based on the circuit diagram.

Abstract: Energy conversion systems that may employ control grid electrodes, acceleration grid electrodes, inductive elements, multi-stage anodes, and emissive carbon coatings on the cathode and anode are described. These and other characteristics may allow for advantageous thermal energy to electrical energy conversion.

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

Abstract: Quantum circuits are synthesized based on a projective gate set derived from a set of single-qubit gates, typically a basis set such as the Clifford+T gates or the V-gates. An initial projective gate set is used to determine at least one characteristic of a quaternion algebra, and the quaternion algebra is used to define a new projective gate set. Exactly synthesizable unitaries are identified, and a circuit approximating a target unitary is defined in the single-qubit gate set by mapping from the new projective gate set.

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes obtaining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding at least one first-in-first-out (FIFO) buffer to at least one of the communication channels, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: Verifying a quantum circuit layout design is provided. A qubit layout is received as input. The qubit layout is generated from a qubit schematic. The qubit schematic includes a plurality of qubits, a plurality of coupling buses, a plurality of readout buses, and a plurality of readout ports. Design rules checking is performed on the qubit layout input, using a predefined set of design rule. The bus style/frequency and qubit information are extracted from the qubit layout input. A new qubit schematic is generated from the extracted bus style/frequency and qubit information. The qubit layout is verified based on the new qubit schematic being the same as the qubit schematic.

Abstract: Generating a layout for a multi-qubit chip is provided. A schematic is received as input. The schematic input includes a plurality of qubits, a plurality of coupling busses, a bus design parameter specifying a bus frequency, a plurality of readout busses, and a plurality of readout ports. A qubit design is selected from a qubit library, based on the qubit style in the schematic input. A bus style is selected from a bus information library, based on the bus style in the schematic input. A qubit layout is automatically generated by assembling the selected bus style/, selected qubit design, the plurality of readout busses and the plurality of readout ports.

Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.

Abstract: There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

Abstract: An overlay architecture and an associated method that uses datapath merging to provide minimal-overhead support for multiple source netlists, and optionally provides an adjustable amount of flexibility through a secondary interconnect network is disclosed.

Abstract: A netlist of a circuit design includes an interface portion and a main portion. The interface portion is decomposed into multiple levels. Each level specifies connections between a respective first set of circuit elements and a respective second set of circuit elements. The second set of circuit elements in each level, except a last level, includes the first set of circuit elements in a next level. The first set of circuit elements identified in a first level of the multiple levels have fixed locations. The second set of circuit elements in the multiple levels is placed-and-routed. The placing-and-routing of the second set of circuit elements in one level is completed before commencing placing-and-routing of the second set of circuit elements in the next level. The main portion is placed-and-routed after placing-and-routing the second set of circuit elements in the multiple levels.

Abstract: Energy conversion systems that may employ control grid electrodes, acceleration grid electrodes, inductive elements, multi-stage anodes, and emissive carbon coatings on the cathode and anode are described. These and other characteristics may allow for advantageous thermal energy to electrical energy conversion.

Abstract: A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.

Abstract: Provided is a stereoscopic display device, including: a base member transmitting an incident beam; and a three-dimensional effect forming part on a first surface of the base member, wherein the three-dimensional effect forming part has a pattern, the pattern having multiple pattern units arranged in a concentric circular, elliptical or polygonal radial form, each of the pattern units having an inclined surface having an inclination angle with respect to the first surface, and wherein when an incident beam is incident to a central portion of the pattern, the pattern guides the incident beam in a first surface direction toward which the first surface looks or a second surface direction toward which a second surface opposite to the first surface looks, thereby displaying a line-shaped beam having a three-dimensional effect in a first path resulting a pattern arrangement direction.

Abstract: An exemplary system for wrapping an intellectual property core (IP) bus master(s), can include, for example, a plurality of IP cores associated with the IP core bus master(s), and a wrapper module connected to a serial input of the IP core bus master(s) and a serial output of the IP core bus master(s), where the wrapper module can be configured to capture and shift a plurality of values of a system bus for a plurality of bus transfers associated with the IP core bus master(s) and the IP cores. The wrapper module can be further configured to modify a wrapper control logic and a wrapper boundary register of the IP core bus master(s). A plurality of terminals can be included, which can be coupled to the IP core bus master(s), and a plurality of wrapper cells can be included, which can be associated with the plurality of terminals.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A method for designing a system on a target device includes identifying components in a netlist that perform a division operation. The netlist is modified during synthesis to utilize other components to compute a result of the division operation by performing a multiplication operation.

Abstract: Generating delays for a clock circuit includes, determining, using a processor, groups of contexts for exit points of the clock circuit based upon a plurality of characteristics and a type selected from a plurality of different types for each characteristic, forming, using the processor, sub-groups of the exit points based upon delay values for the exit points, and determining, using the processor, a mean delay value for each sub-group.

Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

Abstract: A computer-implemented system for generating test cases and/or test procedures to verify software having a nonlinear arithmetic constraint over a Real number range. The system includes a translator that receives, as input, software specification models for the software to be verified. The translator is configured to generate, as output, a plurality of SMT formulas that are semantically equivalent to the software specification models. The system includes an analytical engine pool that receives, as input, the plurality of SMT formulas from the translator and analyzes the plurality of SMT formulas, and generates, as output, test case data for each of the plurality of SMT formulas determined to be satisfiable. The system includes a post-processor that receives, as input, the test case data from the analytical engine pool and generates, as output, the test cases and/or test procedures for the software to be verified based on the test case data.

Abstract: Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.

Abstract: A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.

Abstract: A method includes analyzing a given application to determine one or more packages utilized by the given application, the one or more packages comprising a plurality of libraries, identifying a subset of the plurality of libraries utilized by the given application, determining one or more dependent libraries for each of the identified libraries in the subset, generating a given container for the given application, the given container comprising the identified libraries in the subset and the dependent libraries for each of the identified libraries, performing risk analysis for the given container including comparing a risk value calculated for the given container to a designated risk threshold, simulating one or more actions in the given container responsive to the risk value calculated for the given container exceeding the designated risk threshold, and determining whether to accept or reject the given container responsive to the risk analysis and simulated actions.

Abstract: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.

Abstract: A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical fins. A work function metal (WFM) layer is disposed on the dielectric layer. A first sidewall spacer and a second sidewall space are formed proximate to the first vertical fin and the second vertical fin, respectively. A lithographic mask is applied to a first area proximate to the first vertical fin including the first vertical fin, and a portion of the WFM layer proximate to the first vertical fin. A portion of the WFM layer proximate to the second sidewall spacer is recessed below an upper surface of the second sidewall spacer. The lithographic mask is removed. A portion of the dielectric layer is removed to produce a wimpy vertical transport device and a nominal vertical transport device on the substrate structure.

Abstract: A method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.

Abstract: Solving a multidimensional multicriteria optimization problem is difficult because the correlations and dependencies between solutions, target functions, and variation variables can be detected only with difficulty. In order to facilitate this, it is proposed that a model space (1) and a variation space (2) are displayed simultaneously and in an interactively linked fashion.

Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.