Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

Abstract: Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a transistor device of the plurality of transistor devices creates a design rule violation, determining whether a force mode input has been received. The example method further includes, responsive to determining that the force mode input has been received, enabling routing of the first connection input.

Abstract: Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Abstract: A method for manufacturing a semiconductor device to which corresponds a layout diagram stored on a non-transitory computer-readable medium. The method includes generating the layout diagram using an electronic design system (EDS), the EDS including at least one processor and at least one memory including computer program code for one or more programs are configured to cause the EDS to execute the generating. Testing the semiconductor device. Revising, the layout diagram, based on testing results indicative of selected standard functional cells in the layout diagram which merit modification or replacement. Programming one or more of the ECO cells which correspond to the one or more selected standard functional cells resulting in one or more programmed ECO cells. Routing the one or more programmed ECO cells correspondingly to at least one of the selected standard functional cells or to one or more other ones of the standard functional cells.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

Abstract: Disclosed are a method and an apparatus for string connecting photovoltaic modules. The method includes: acquiring position information of n photovoltaic modules to be connected; categorizing the n photovoltaic modules into m partitions based on the position information of the n photovoltaic modules; generating k candidate connection solutions of an ith partition in the m partitions, wherein the ith partition includes m photovoltaic modules, and each of the k candidate connection solutions uses one photovoltaic module in the m photovoltaic modules as a starting point, and obtaining at least one string of photovoltaic modules by simulating connection of the m photovoltaic modules according to a preset connection solution; and selecting a target connection solution from the k candidate connection solutions based on an estimated cable use amount corresponding to each of the k candidate connection solutions.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

Abstract: One aspect of this description relates to an integrated circuit (IC) structure including a first layer and a second layer. The first layer includes a first metal structure coupled to a first power supply having a first voltage level and a second metal structure coupled to a second power supply having a second voltage level different from the first voltage level. The second layer is formed over the first layer. The second layer includes a first nano-sheet device coupled to the first metal structure and a second nano-sheet device adjacent to the first nano-sheet device. The second nano-sheet device is coupled to the second metal structure. A distance between the first nano-sheet device and the second nano-sheet device is less than a minimum n-well to n-well spacing.

Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Abstract: Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2?m<PPG and PPG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch PPG>m*P.

Abstract: An integrated circuit structure includes a first and second power rail extending in a first direction and being located at a first level, a first and second set of conductive structures located at a second level and extending in a second direction, a first and second set of vias, and a first and second conductive structure located at a third level and extending in the second direction. The first set of vias coupling the first power rail to the first set of conductive structures. The second set of vias coupling the second power rail to the second set of conductive structures. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and the second set of conductive structures.

Abstract: A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area.

Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

Abstract: An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

Abstract: According to one or more embodiments, a semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate and a plurality of transistors on the semiconductor substrate. The second chip includes a memory cell array and a plurality of first patterns. The memory cell array is connected to the plurality of transistors of the first chip and includes a plurality of memory blocks arranged in a first direction. The plurality of first patterns are spaced from each other in the first direction. Each first pattern represents a different number and is at a position corresponding to one or more of the memory blocks.

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each die of a plurality of dice in the power network, a first signal indicating that the respective die of the plurality of dice is in a high current state or a second signal indicating that the respective die of the plurality of dice is an active current state. The received signals include at least one second signal. The first die determines, based upon the received signals, a number of dice of the plurality of dice that are currently active and selects an activity threshold based upon that number. The first die further determines an activity level for the power network and transmits, to the plurality of dice, the first signal indicating that the first die is in the high current state in response to determining that the activity level is less than the activity threshold.

Abstract: An optimization engine determines an optimal configuration for a solar power system projected onto a target surface. The optimization engine identifies an alignment axis that passes through a vertex of a boundary associated with the target surface and then constructs horizontal or vertical spans that represent contiguous areas where solar modules may be placed. The optimization engine populates each span with solar modules and aligns the solar modules within adjacent spans to one another. The optimization engine then generates a performance estimate for a collection of populated spans. By generating different spans with different solar module types and orientations, the optimization engine is configured to identify an optimal solar power system configuration.

Abstract: In an information processing device according to the present invention, a statistics estimation unit estimates a value of a state quantity by using a statistical model constructed based on values of past state quantities of a target device. A physical estimation unit estimates a value of a state quantity by using a physical model constructed based on design data of the target device. A specification unit specifies a value to be used to manage the target device from the value estimated by the statistics estimation unit and the value estimated by the physical estimation unit based on deterioration of the target device with time.

Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of

Abstract: A system can include a memory device and a processing device to perform operations that include identifying voltage offset bins of the memory device, each of the first voltage offset bins satisfying a first age threshold criterion, identifying one or more second voltage offset bins of the memory device, each of the second voltage offset bins satisfying a second age threshold criterion, identifying a first block family associated with one of the first voltage offset bins, and performing a first scan of a first block of the first block family by: identifying, based on determined values of the first data state metric, a first identified voltage offset bin, and identifying one or more values of a second data state metric in scan metadata generated by a second scan, and identifying, based on the one or more values of the second data state metric, a second identified voltage offset bin.

Abstract: An automated system and method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The system operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The system inspects the various devices and automatically traces DC circuit paths to DC power rails. The system then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The system generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable combinational logic for the gated clock, as a disjunction of the enable combinational logic of the gated clock and an enable combinational logic for each FF of a plurality of FFs that are toggled by the gated clock. The method also includes performing SEC on the two representations design, using the modified enable combinational logic for the gated clock instead of the enable combinational logic of the gated clock.

Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

Abstract: Disclosed is an integrated circuit (IC) layout method capable of reducing an IR drop as a result of an IC layout process. The method includes the following steps: performing the IC layout process and obtaining an original IC layout; performing an IR drop analysis on the original IC layout and identifying an IR drop hot zone; determining a circuit density limit of the IR drop hot zone; and performing the IC layout process again according to the circuit density limit and obtaining an updated IC layout.

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a second voltage supply having a second supply voltage different from the first supply voltage.

Abstract: A method is disclosed and includes forming a plurality of dummy conductive cells that provides different densities in empty areas in metal layers of a semiconductor device according to overlap conditions of the empty areas each arranged between a pair of neighboring metal layers of metal layers. Forming the plurality of dummy conductive cells includes operations of forming a group of dummy conductive cells in a single empty area of the empty areas when the single empty area in one pair of the neighboring metal layers is overlapped by a signal line in the same pair of the neighboring metal layers. When viewed in plan view, projection areas of the group of dummy conductive cells are vertically overlapped by a projection area of the signal line. A semiconductor device is also disclosed herein.

Abstract: A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

Abstract: A computer-implemented method and a computing system for designing an integrated circuit are provided. The method includes generating wire data corresponding to a net included in an integrated circuit, the wire data including metal layer information of a wire corresponding to the net and physical information of the wire, performing timing analysis using the physical information of the wire included in the wire data to generate timing analysis data, and changing a layout of the integrated circuit according to the timing analysis data.

Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: A system and method for creating chip layout are described. In various embodiments, a standard cell uses unidirectional tracks for power connections and signal routing. At least two tracks of the metal one layer using a minimum width of the metal one layer are placed within a pitch of a single metal gate to provide a standard cell with a two to one “gear ratio” or greater. A power signal and a ground reference signal in the metal one layer are routed in a same metal one track to provide area for other signal routing. Multiple standard cells are placed in a multi-cell layout with routes in one or more of the metal two layer and the metal three layer using minimum lengths for power connections. The layout includes no power grid with a fixed pitch.

Abstract: The invention discloses a clock tree synthesis method including steps of: determining a driving strength of a clock cell; determining a reserved space corresponding to the clock cell according to the driving strength; generating the clock cell and the reserved space, wherein the reserved space is adjacent to the clock cell; setting a decoupling capacitor filler cell in the reserved space, wherein the area and/or capacitance of the decoupling capacitor filler cell are/is associated with the driving strength; and fixing the attribute(s) of the clock cell and the attribute(s) of the decoupling capacitor filler cell.

Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided. The integrated circuit package includes a first die manufactured on a first wafer utilizing a first node size, a second die manufactured on a second wafer utilizing a second node size, and a substrate coupled to the second die at a plurality of bump sites on a bottom surface of the second die. The first die may be mounted on a top surface of the second die utilizing a hybrid wafer bonding technique, micro bumps, or electrode-less plating.

Abstract: A method of manufacturing an IC includes detecting connectivity between polygons from layout data of the IC and extracting a layout netlist, by performing a DRC on the layout data. The DRC includes loading a rule file including a DRC syntax. The method includes performing LVS verification on the extracted layout netlist and schematic data of the IC to generate LVS result data. The method includes manufacturing the IC according to a layout based on the layout data and the LVS result data.

Abstract: An optimization engine determines an optimal configuration for a solar power system projected onto a target surface. The optimization engine identifies an alignment axis that passes through a vertex of a boundary associated with the target surface and then constructs horizontal or vertical spans that represent contiguous areas where solar modules may be placed. The optimization engine populates each span with solar modules and aligns the solar modules within adjacent spans to one another. The optimization engine then generates a performance estimate for a collection of populated spans. By generating different spans with different solar module types and orientations, the optimization engine is configured to identify an optimal solar power system configuration.

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.