Floorplanning Patents (Class 716/118)
  • Patent number: 12112829
    Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ying Lee, Chia-En Huang, Meng-Sheng Chang
  • Patent number: 12058847
    Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Abhishek A. Sharma, Charles Kuo, Brian S. Doyle, Urusa Shahriar Alaan, Van H Le, Elijah V. Karpov, Kaan Oguz, Arnab Sen Gupta
  • Patent number: 12001772
    Abstract: Semiconductor integrated circuit devices are provided which have standard cells with ultra-short standard cell heights. For example, a device comprises an integrated circuit comprising a standard cell which comprises a first cell boundary and a second cell boundary. The standard cell comprises an n-track cell height defined by a distance between the first cell boundary and the second cell boundary, wherein n is four or less.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Albert Chu, Junli Wang, Brent Anderson
  • Patent number: 11736410
    Abstract: An example controller device that manages a plurality of network devices includes one or more processors implemented in circuitry and configured to: determine that configuration of one or more network devices of the plurality of network devices is to be updated; determine dependencies between types of resources provided by the network devices; construct a directed acyclic graph (DAG) representing the dependencies, the DAG having nodes representing the corresponding types of resources of the network devices of the plurality of network devices; sort the nodes of the DAG according to a grouped topological sort into a plurality of hierarchical levels according to the dependencies; and submit queries for two or more resources of the network devices at a common level of the plurality of hierarchical levels in parallel to determine resources of the determined types of resources of the two or more resources to configure the two or more network devices.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Juniper Networks, Inc.
    Inventors: Vijaya Kumar Hosamani, Vinaya Kumar Kathireddy, Adithya Shasa Sai Seerapu
  • Patent number: 11720732
    Abstract: Embodiments of the invention are directed to a computer-implemented method of determining timing constraints of a first component-under-design (CUD). The computer-implemented method includes accessing, using a processor, a plurality of timing constraint requirements configured to be placed on the first CUD by one or more second CUDs, wherein each of the plurality of timing constraint requirements is specifically designed for the CUD. The processor is used to perform a comparative analysis of each of the plurality of timing constraints to identify a single timing constraint that satisfies each of the plurality of timing constraints.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: August 8, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chris Aaron Cavitt, Brandon Albert Bruen, Eric Foreman, Jesse Peter Surprise
  • Patent number: 11675726
    Abstract: A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes, based on the annotated first bus guide and the second bus guide, generating, by at least one processor, a plurality of guidance directories corresponding to a plurality of routes through the plurality of layout blocks for placing the plurality of repeaters at the plurality of layout blocks on the identified plurality of areas on the first bus guide or the second bus guide.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: June 13, 2023
    Assignee: Synopsys, Inc
    Inventors: Kai-Ping Wang, Songmei Chen, Ying Liu, Xiaolin Yuan
  • Patent number: 11645441
    Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: May 9, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bentian Jiang, Natarajan Viswanathan, Zhuo Li, Yi-Xiao Ding
  • Patent number: 11568633
    Abstract: A computer-implemented method for comparing a first version of a floorplan of a design for an integrated circuit with a second version. The method comprises (i) generating a timing information for each net in the second version by determining whether timing information is available for the net in the first version; (ii) in case no timing information is available in the first version, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; (iii) otherwise, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Siegmund Schlechter, Manuel Beck
  • Patent number: 11455448
    Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shen Lin, Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee
  • Patent number: 11144228
    Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Martinelli, Christophe Vincent Antoine Laurent, Claudio Nava, Marco Defendi
  • Patent number: 11120191
    Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: Arm Limited
    Inventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
  • Patent number: 11094685
    Abstract: A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11037920
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen
  • Patent number: 10977410
    Abstract: A switch box approach to routing interconnects during the design of an integrated circuit (IC). Processing circuitry (e.g., via an automation tool) may determine a manner in which to interconnect functional blocks of the IC. The signal routes that interconnect the functional blocks can become complicated to comply with design rules for latency, crosstalk, etc. The processing circuitry may divide channels between functional blocks into multiple interconnection blocks, called channel blocks. In this way, the channel blocks may be considered as another block type (e.g., interconnection block) that the processing circuitry can leverage for routing signals between functional blocks.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: April 13, 2021
    Assignee: Fungible, Inc.
    Inventors: Vijaykumar I. Patel, Bharat K. Bisen
  • Patent number: 10867114
    Abstract: An integrated circuit (IC) structure includes a first active region, a second active region, a first multi-gate structure, a first rail and a second rail. The first active region and the second active region extend in a first direction and are located at a first level. The second active region is separated from the first active region in a second direction. The first multi-gate structure extends in the second direction, overlaps the first active region and the second active region, and is located at a second level different from the first level. The first rail extends in the first direction, overlaps a portion of the first active region, supplies a first supply voltage, and is located at a third level. The second rail extends in the first direction, is located at the third level, is separated from the first rail in the second direction, and supplies a second supply voltage.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Zhong Zhuang, Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen
  • Patent number: 10790272
    Abstract: Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes two-dimensional (2D) shapes; a second layer coupled adjacent to the first layer through at least one via hole, wherein the second layer includes only one-dimensional (1D) shapes; a shared drain terminal; and a source terminal termination.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Harmeet Sobti, Mehrdad Manesh, Li-Fu Chang
  • Patent number: 10747935
    Abstract: A method of performing physical design of an integrated circuit includes subdividing each metal layer of a plurality of metal layers of the integrated circuit into a plurality of g-cells. Each metal layer has either horizontal or vertical tracks, the g-cells of the metal layers with horizontal tracks have vertical edges between adjacent ones of the g-cells, and the g-cells of the metal layers with vertical tracks have horizontal edges between adjacent ones of the g-cells. The method includes determining congestion for each metal layer as congestion values associated with the horizontal edges or the vertical edges of the metal layer, identifying hotspots for each metal layer based on the congestion values of the metal layer, determining a penalty associated with the hotspots of each metal layer, determining a congestion metric for each metal layer based on the penalty, and performing routing of the wires based on the congestion metric.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhichao Li, Yaoguang Wei, Diwesh Pandey, Gustavo Enrique Tellez
  • Patent number: 10634992
    Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 28, 2020
    Assignee: Synopsys, Inc.
    Inventor: Ralph Iverson
  • Patent number: 10599806
    Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 24, 2020
    Assignee: Arm Limited
    Inventors: Xiaoqing Xu, Brian Tracy Cline, Stephen Lewis Moore, Saurabh Pijuskumar Sinha
  • Patent number: 10579767
    Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: March 3, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhuo Li, Wen-Hao Liu, Gracieli Posser, Charles Jay Alpert, Ruth Patricia Jackson
  • Patent number: 10559558
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a wire cut between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the wire cut separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen
  • Patent number: 10484880
    Abstract: A method performed by an apparatus is presented which comprises determining one or more potential installation positions and/or areas for installing one or more radio positioning support devices in a predetermined environment, wherein said one or more potential installation positions and/or areas are determined at least partially based on at least one radio coverage model.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 19, 2019
    Assignee: HERE Global B.V.
    Inventors: Jari Tapani Syrjärinne, Muhammad Irshan Khan, Pavel Ivanov, Lauri Aarne Johannes Wirola
  • Patent number: 10474038
    Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
  • Patent number: 10460070
    Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Shen Lin, Ching-Shun Yang, Hsien Yu-Tseng
  • Patent number: 10452452
    Abstract: Disclosed techniques utilize a satisfiability solver for allocation and/or configuration of resources in a reconfigurable fabric of processing elements. A dataflow graph is an input provided to a toolchain that includes a satisfiability solver. The satisfiability solver operates on subsets of interconnected nodes within a dataflow graph to derive a solution. The solution is trimmed by removing artifacts and unnecessary parts. The solutions of subsets are then used as an input to additional subsets of nodes within the dataflow graph in an iterative process to derive a complete solution. The satisfiability solver technique uses adaptive windowing in both the time dimension and the spatial dimensions of the dataflow graph. Processing elements and routing elements within the reconfigurable fabric are configured based on the complete solution. Data computation is performed based on the dataflow graph using the processing elements and the routing resources.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 22, 2019
    Assignee: Wave Computing, Inc.
    Inventors: Asmus Hetzel, Samit Chaudhuri
  • Patent number: 10431545
    Abstract: A multi-chip module includes two silicon bridge interconnects and three components that are tied together by the bridges with one of the components in the center. At least one of the silicon bridge interconnects is bent to create a non-planar chip-module form factor. Cross-connected multi-chip silicon bent-bridge interconnect modules include the two silicon bridges contacting the center component at right angles to each other, plus a fourth component and a third silicon bridge interconnect contacting the fourth component and any one of the original three components.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Bernd Waidhas, Thomas Wagner, Andreas Wolter, Laurent Millou
  • Patent number: 10418549
    Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: September 17, 2019
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Nianduan Lu, Pengxiao Sun, Ling Li, Ming Liu, Qi Liu, Hangbing Lv, Shibing Long
  • Patent number: 10354039
    Abstract: Disclosed are techniques for implementing legal placement with contextual awareness for an electronic design. These techniques identify one or more hierarchies from one or more groups or one or more instances located at these one or more hierarchies in a layout or floorplan. A plurality of instances including the one or more identified instances may be promoted to an honorary top hierarchy. A layout operation may then be performed on the one or more identified instances based in part or in whole upon a boundary requirement and context information.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Vinny George Korah
  • Patent number: 10331841
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 25, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Jean-Noel Pic
  • Patent number: 10325050
    Abstract: A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 18, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mani Viswanath, Thomas Mitchell, John Eitrheim
  • Patent number: 10303837
    Abstract: Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 28, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: James Lewis Nance, Jun Chen, Gary B. Nifong
  • Patent number: 10289789
    Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10274829
    Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Pai-Wei Wang, Ru-Gun Liu, Chih-Ming Lai
  • Patent number: 10216882
    Abstract: A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinwook Jung, Frank Musante, Gi-Joon Nam, Shyam Ramji, Lakshmi Reddy, Gustavo Tellez, Cindy S. Washburn
  • Patent number: 10192020
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing dynamic maneuvers within virtual hierarchies of an electronic design. These techniques identify or generate a plurality of figure groups at one or more virtual hierarchies in a layout portion and receive a request to descend into or ascend from a figure group at a virtual hierarchy of the one or more virtual hierarchies. In response to the received request, these techniques update a layout view into an updated layout view at least by exposing layout design details in the figure group for native editing according to the request to descend into or ascend from the figure group and optionally synchronize a corresponding schematic design view according to the updated layout view.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 10181004
    Abstract: Systems and methods are provided for identifying a wire of a plurality of wires to be adjusted to mitigate effects of electromigration. A method includes identifying a plurality of wires of a circuit, each wire comprising a one or more wire segments. An electromigration stress is determined for each wire path of each wire, a wire path being made up of one or more wire segments. For each wire, a highest determined electromigration stress is assigned for wire paths of that wire as the wire electromigration stress for that wire. An identification of the wire having the highest wire electromigration stress is stored, where the wire having the highest wire electromigration stress is a candidate for adjustment to mitigate electromigration effects.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 15, 2019
    Assignee: Ansys, Inc.
    Inventor: Craig Larsen
  • Patent number: 10162930
    Abstract: A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Lin, Kam-Tou Sio, Shih-Wei Peng, Hui-Ting Yang′, Chih-Liang Chen, Jiann-Tyng Tzeng, Chew-Yuen Young, Chia-Tien Wu, Chih-Ming Lai
  • Patent number: 10158017
    Abstract: A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third and fourth epitaxial semiconductor features are at least partially embedded in the substrate. A first proximity of the third epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the fourth epitaxial semiconductor features to the respective second gate structures. In an embodiment, a first depth of the third epitaxial semiconductor features embedded into the substrate is greater than a second depth of the fourth epitaxial semiconductor features embedded into the substrate.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Tzu-Hsiang Hsu, Ting-Yeh Chen, Feng-Cheng Yang
  • Patent number: 10101761
    Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 16, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Issei Kashima, Jingo Nakanishi
  • Patent number: 10002224
    Abstract: Embodiments relate to an interactive routing of connections in a circuit wherein the connections associated with an initial pin of a circuit element (e.g., a row of FinFETs) are replicated in association with at least one other pin of the same circuit element or a different circuit element in the circuit. Replication of connections is performed intelligently by taking into account mapping of pins as well as imposing design rules or other restrictions on the circuit. The connections are in the form of trunks and branches, and are displayed as user inputs are received. A digital representation of the circuit with the connections as displayed is also generated. At least some of the connections in the circuit are replicated without individual user inputs based on user inputs associated with a connection to the initial pin.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 19, 2018
    Assignee: Synopsys, Inc.
    Inventors: Philippe Aubert McComber, Hsiang-Wen Jimmy Lin
  • Patent number: 9853112
    Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: December 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Yanxiang Liu, Stanley Seungchul Song, Kern Rim
  • Patent number: 9811626
    Abstract: A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwangok Jeong
  • Patent number: 9747406
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 29, 2017
    Assignee: Synopsys, Inc.
    Inventors: Chien-Hung Lu, Chun-Cheng Chi, Tung-Chieh Chen
  • Patent number: 9734276
    Abstract: A method of designing a layout of an integrated circuit (IC) includes: preparing a standard cell library that stores a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including a plurality of conductive lines that extend in a first direction, placing the first standard cell and the second standard cell to be adjacent to each other in a first boundary parallel to the plurality of conductive lines, and generating a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is applied to a first pattern adjacent to the first boundary in the first standard cell and a second pattern adjacent to the first boundary in the second standard cell, the at least one first conductive line being adjacent to the first boundary.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-tae Kim, Chang-beom Kim
  • Patent number: 9659123
    Abstract: Circuit design equipment may design logic for a circuit. The design equipment may discover optimized design constraints and an optimized clock signal frequency for the circuit. The design equipment may output the discovered optimized clock signal frequency and design constraints to circuit fabrication equipment for fabricating the corresponding circuit. The design equipment may discover the optimized clock signal frequency and design constraints by populating a cost function with different clock signal frequencies and different design constraint values. The cost function may be, for example, a multi-dimensional surface. The design equipment may identify a global minimum of the cost function and may identify the clock signal frequency and design constraint values that correspond to the global minimum as the optimized clock frequency and optimized design constraints to provide to circuit fabrication equipment.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 23, 2017
    Assignee: 21, Inc.
    Inventors: Veerbhan Kheterpal, Daniel Firu, Nigel Drego
  • Patent number: 9639648
    Abstract: Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 2, 2017
    Assignee: SYNOPSYS, INC.
    Inventor: Aydin O. Balkan
  • Patent number: 9582462
    Abstract: A computer system has a plurality of computer servers, each including at least one central processing unit (CPU). A memory appliance is spaced remotely from the plurality of computer servers. The memory appliance includes random access memory (RAM). A photonic CPU link is operatively attached to the at least one CPU. An optical-electrical converter is operatively attached to the photonic CPU link. An electronic circuit switch is operatively attached to the optical-electrical converter and the memory appliance. An allocated portion of the RAM is addressable by a predetermined CPU selected from the plurality of computer servers.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 28, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Terrel Morris
  • Patent number: 9551923
    Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Sen Wang, Ming-Yi Lin, Chen-Hung Lu, Jyh-Kang Ting
  • Patent number: 9411923
    Abstract: An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and have manufactured a specific class of custom electronic device, namely a computer processing unit with embedded software. A Graphical User Interface (GUI) is provided as the front-end to a Computer Aided Design (CAD) server that generates sophisticated control and manufacturing instructions that are delivered to a fabrication supply chain, which produces a specified device that is then transported via managed logistics into inventory and ordering systems at vendors for delivery to a designated customer.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 9, 2016
    Assignee: Gumstix, Inc.
    Inventors: Walter Gordon Kruberg, Neil C. MacMunn
  • Patent number: 9396297
    Abstract: Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device. The flat transistor is formed by an active region defined by an isolation region on a semiconductor substrate, a gate electrode extending from the isolation region across the active region, and an impurity region in a portion of the active region. The first corner transistor is formed by an overlapping of the gate electrode and a first edge portion of the active region.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Mi-Hyun Kang