Floorplanning Patents (Class 716/118)
  • Patent number: 10418549
    Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: September 17, 2019
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Nianduan Lu, Pengxiao Sun, Ling Li, Ming Liu, Qi Liu, Hangbing Lv, Shibing Long
  • Patent number: 10354039
    Abstract: Disclosed are techniques for implementing legal placement with contextual awareness for an electronic design. These techniques identify one or more hierarchies from one or more groups or one or more instances located at these one or more hierarchies in a layout or floorplan. A plurality of instances including the one or more identified instances may be promoted to an honorary top hierarchy. A layout operation may then be performed on the one or more identified instances based in part or in whole upon a boundary requirement and context information.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 16, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Yu, Vinny George Korah
  • Patent number: 10331841
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing virtual prototyping for electronic designs. These techniques identify a plurality of leaf cells into a hierarchical physical design of an electronic design, generate the hierarchical physical design at least by performing hierarchical placement for the plurality of leaf cells based in part or in whole upon one or more factors, and revise the placed hierarchical physical design at least by performing hierarchical routing for the plurality of leaf cells on the hierarchical physical design. One aspect may further detach a virtual cell in the hierarchical physical design at least by grouping a first set of leaf cells and representing the first set of leaf cells with a first placeholder.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 25, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Jean-Noel Pic
  • Patent number: 10325050
    Abstract: A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 18, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mani Viswanath, Thomas Mitchell, John Eitrheim
  • Patent number: 10303837
    Abstract: Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: May 28, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: James Lewis Nance, Jun Chen, Gary B. Nifong
  • Patent number: 10289789
    Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 10274829
    Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Wen-Li Cheng, Pai-Wei Wang, Ru-Gun Liu, Chih-Ming Lai
  • Patent number: 10216882
    Abstract: A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinwook Jung, Frank Musante, Gi-Joon Nam, Shyam Ramji, Lakshmi Reddy, Gustavo Tellez, Cindy S. Washburn
  • Patent number: 10192020
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing dynamic maneuvers within virtual hierarchies of an electronic design. These techniques identify or generate a plurality of figure groups at one or more virtual hierarchies in a layout portion and receive a request to descend into or ascend from a figure group at a virtual hierarchy of the one or more virtual hierarchies. In response to the received request, these techniques update a layout view into an updated layout view at least by exposing layout design details in the figure group for native editing according to the request to descend into or ascend from the figure group and optionally synchronize a corresponding schematic design view according to the updated layout view.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 29, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 10181004
    Abstract: Systems and methods are provided for identifying a wire of a plurality of wires to be adjusted to mitigate effects of electromigration. A method includes identifying a plurality of wires of a circuit, each wire comprising a one or more wire segments. An electromigration stress is determined for each wire path of each wire, a wire path being made up of one or more wire segments. For each wire, a highest determined electromigration stress is assigned for wire paths of that wire as the wire electromigration stress for that wire. An identification of the wire having the highest wire electromigration stress is stored, where the wire having the highest wire electromigration stress is a candidate for adjustment to mitigate electromigration effects.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 15, 2019
    Assignee: Ansys, Inc.
    Inventor: Craig Larsen
  • Patent number: 10162930
    Abstract: A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Lin, Kam-Tou Sio, Shih-Wei Peng, Hui-Ting Yang′, Chih-Liang Chen, Jiann-Tyng Tzeng, Chew-Yuen Young, Chia-Tien Wu, Chih-Ming Lai
  • Patent number: 10158017
    Abstract: A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third and fourth epitaxial semiconductor features are at least partially embedded in the substrate. A first proximity of the third epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the fourth epitaxial semiconductor features to the respective second gate structures. In an embodiment, a first depth of the third epitaxial semiconductor features embedded into the substrate is greater than a second depth of the fourth epitaxial semiconductor features embedded into the substrate.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Tzu-Hsiang Hsu, Ting-Yeh Chen, Feng-Cheng Yang
  • Patent number: 10101761
    Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 16, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Issei Kashima, Jingo Nakanishi
  • Patent number: 10002224
    Abstract: Embodiments relate to an interactive routing of connections in a circuit wherein the connections associated with an initial pin of a circuit element (e.g., a row of FinFETs) are replicated in association with at least one other pin of the same circuit element or a different circuit element in the circuit. Replication of connections is performed intelligently by taking into account mapping of pins as well as imposing design rules or other restrictions on the circuit. The connections are in the form of trunks and branches, and are displayed as user inputs are received. A digital representation of the circuit with the connections as displayed is also generated. At least some of the connections in the circuit are replicated without individual user inputs based on user inputs associated with a connection to the initial pin.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 19, 2018
    Assignee: Synopsys, Inc.
    Inventors: Philippe Aubert McComber, Hsiang-Wen Jimmy Lin
  • Patent number: 9853112
    Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: December 26, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Yanxiang Liu, Stanley Seungchul Song, Kern Rim
  • Patent number: 9811626
    Abstract: A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwangok Jeong
  • Patent number: 9747406
    Abstract: A computer implemented method of routing a net of an electronic circuit is disclosed. The net connects a plurality of pins of the electronic circuit. The method includes selecting, using one or more computer systems, first and second main spine routing tracks for respective first and second groups of pins of the net. The method also includes generating, using one or more computer systems, a first main spine wire on the selected first main spine routing track and a second main spine wire on the selected second main spine routing track. A router configured to perform the method is also disclosed.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 29, 2017
    Assignee: Synopsys, Inc.
    Inventors: Chien-Hung Lu, Chun-Cheng Chi, Tung-Chieh Chen
  • Patent number: 9734276
    Abstract: A method of designing a layout of an integrated circuit (IC) includes: preparing a standard cell library that stores a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including a plurality of conductive lines that extend in a first direction, placing the first standard cell and the second standard cell to be adjacent to each other in a first boundary parallel to the plurality of conductive lines, and generating a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is applied to a first pattern adjacent to the first boundary in the first standard cell and a second pattern adjacent to the first boundary in the second standard cell, the at least one first conductive line being adjacent to the first boundary.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-tae Kim, Chang-beom Kim
  • Patent number: 9659123
    Abstract: Circuit design equipment may design logic for a circuit. The design equipment may discover optimized design constraints and an optimized clock signal frequency for the circuit. The design equipment may output the discovered optimized clock signal frequency and design constraints to circuit fabrication equipment for fabricating the corresponding circuit. The design equipment may discover the optimized clock signal frequency and design constraints by populating a cost function with different clock signal frequencies and different design constraint values. The cost function may be, for example, a multi-dimensional surface. The design equipment may identify a global minimum of the cost function and may identify the clock signal frequency and design constraint values that correspond to the global minimum as the optimized clock frequency and optimized design constraints to provide to circuit fabrication equipment.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 23, 2017
    Assignee: 21, Inc.
    Inventors: Veerbhan Kheterpal, Daniel Firu, Nigel Drego
  • Patent number: 9639648
    Abstract: Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: May 2, 2017
    Assignee: SYNOPSYS, INC.
    Inventor: Aydin O. Balkan
  • Patent number: 9582462
    Abstract: A computer system has a plurality of computer servers, each including at least one central processing unit (CPU). A memory appliance is spaced remotely from the plurality of computer servers. The memory appliance includes random access memory (RAM). A photonic CPU link is operatively attached to the at least one CPU. An optical-electrical converter is operatively attached to the photonic CPU link. An electronic circuit switch is operatively attached to the optical-electrical converter and the memory appliance. An allocated portion of the RAM is addressable by a predetermined CPU selected from the plurality of computer servers.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 28, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Terrel Morris
  • Patent number: 9551923
    Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Sen Wang, Ming-Yi Lin, Chen-Hung Lu, Jyh-Kang Ting
  • Patent number: 9411923
    Abstract: An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and have manufactured a specific class of custom electronic device, namely a computer processing unit with embedded software. A Graphical User Interface (GUI) is provided as the front-end to a Computer Aided Design (CAD) server that generates sophisticated control and manufacturing instructions that are delivered to a fabrication supply chain, which produces a specified device that is then transported via managed logistics into inventory and ordering systems at vendors for delivery to a designated customer.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 9, 2016
    Assignee: Gumstix, Inc.
    Inventors: Walter Gordon Kruberg, Neil C. MacMunn
  • Patent number: 9396297
    Abstract: Provided are an apparatus and a method for simulating a semiconductor device. The method includes: modeling, through an input interface of a simulation device, a flat transistor as a first transistor; modeling, through the input interface, a first corner transistor as a second transistor; and calculating, by a processor of the simulation device, an output electrical signal in response to an input electrical signal applied to the first transistor and the second transistor to simulate at least one electrical characteristic of the semiconductor device. The flat transistor is formed by an active region defined by an isolation region on a semiconductor substrate, a gate electrode extending from the isolation region across the active region, and an impurity region in a portion of the active region. The first corner transistor is formed by an overlapping of the gate electrode and a first edge portion of the active region.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Mi-Hyun Kang
  • Patent number: 9355201
    Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 31, 2016
    Assignee: Mentor Graphics Corporation
    Inventor: Yuri Granik
  • Patent number: 9165889
    Abstract: An alignment mark definer is configured to provide a geometrical definition for an actual alignment structure to be formed at a temporary surface of a substrate based on a desired appearance of the alignment mark and on an expected alteration of an appearance of the actual alignment structure caused by a deposition material deposited on the temporary surface and the actual alignment structure.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Joerg Ortner, Josef Campidell, Andreas Greiner
  • Patent number: 9043740
    Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Xiaochun Zhu, Xia Li, Seung Hyuk Kang
  • Patent number: 9043737
    Abstract: A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 26, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jayanta Bahadra, Xiushan Feng, Xiao Sun
  • Publication number: 20150143319
    Abstract: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semicondutor Manufacturing Co., Ltd.
    Inventors: Liang-Yao Lee, Tsung-Chieh Tsai, Juing-Yi Wu, Chun-Yi Lee
  • Publication number: 20150102364
    Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 9009637
    Abstract: A method for making a matrix device including a matrix of photodetecting or photoemitting elements, the method including designing operations for: a) identifying, from at least one topology of the matrix device, one or more spurious conducting closed circuits; b) selecting at least one photodetecting or photoemitting element of the matrix device belonging to at least one of the spurious conducting closed circuits identified, the at least one element selected being made inactive.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 14, 2015
    Assignees: Commissariat á l'énergie atomique et aux énergies alternatives, ISORG
    Inventors: Christophe Premont, Romain Gwoziecki
  • Patent number: 9009641
    Abstract: A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.
    Type: Grant
    Filed: January 12, 2013
    Date of Patent: April 14, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt, Daryl Fox
  • Patent number: 9009644
    Abstract: A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 14, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Puneet Sharma, Chi-Min Yuan
  • Patent number: 9003336
    Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chun Huang, Ken-Hsien Hsieh, Ming-Hui Chih, Chih-Ming Lai, Ru-Gun Liu, Ko-Bin Kao, Chii-Ping Chen, Dian-Hau Chen, Tsai-Sheng Gau, Burn Jeng Lin
  • Patent number: 9003341
    Abstract: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 9003347
    Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Wu-An Kuo
  • Patent number: 9003346
    Abstract: Techniques for reducing post-routing delay variance are described herein. In an example embodiment, an initial netlist includes multiple instances that represent digital components of an electronic design. An base signature is assigned to each instance in the initial netlist, where the base signature is based on two or more design or connectivity attributes of the instance. The base signatures are then used to generate an initial instance ordering of the instances in the initial netlist. A subsequent netlist, different from the initial netlist but representing the same electronic design, is received. Base signatures are assigned to the instances on the subsequent netlist and a subsequent instance ordering is generated. The subsequent instance ordering preserves the same order as the initial instance ordering for those instances that are included in both the initial netlist and the subsequent netlist. In this manner, any later netlist-based processing (e.g.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 7, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Avijit Dutta, Krishnan Anandh, Steven Danz, Neil Tuttle, Ryan Morse, Haneef Mohammed
  • Patent number: 8987828
    Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 24, 2015
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Deepak D. Sherlekar
  • Publication number: 20150082266
    Abstract: According to one embodiment, a method of designing an input/output circuit which includes input/output cells of a semiconductor device is provided. The method uses a computer which has a schematic generating unit and a layout generating unit. By the schematic generating unit, a symbol of one input/output cell is arranged on a schematic diagram so as to generate schematic data. The symbol has pins including a through pin, a power pin and information indicating power rails. The symbol is capable of being set so as to connect the through pin of the symbol to a pin of a symbol of another input/output cell or to the power pin of the symbol of the one input/output cell itself selectively. After generating the schematic data, the connection is set. Further, layout data is generated by the layout generating unit.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yumiko MIZUTA
  • Patent number: 8984464
    Abstract: A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design and uses a satisfiability solver to resolve placement violations. In some embodiments, the constraints include mathematical expressions that express timing requirements. The method in some embodiments converts the mathematical expressions into Boolean clauses and sends the clauses to a satisfiability solver that is only capable of solving Boolean clauses. In some embodiments, the method groups several cells in the user design and several sites on the IC fabric and uses the satisfiability solver to resolve all placement issues in the group. The satisfiability solver informs placer after each cell is moved to a different site. The method then dynamically builds more constraints based on the new cell placement and sends the constraints to the satisfiability solver.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Tabula, Inc.
    Inventors: Andrew C. Mihal, Steven Teig
  • Patent number: 8978000
    Abstract: The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Mu-Jen Huang, Hsiao-Hui Chen, Cheok-Kei Lei, Po-Tsun Chen, Yu-Sian Jiang
  • Publication number: 20150060939
    Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James P. DI SARRO, Robert J. GAUTHIER, JR., Tom C. LEE, Junjun LI, Souvick MITRA, Christopher S. PUTNAM
  • Patent number: 8966422
    Abstract: A computer implemented method for designing an integrated circuit includes: forming, on a computing device, a description of an initial layout of the integrated circuit, the layout including at least two paths, each of the two paths including an input, an output and an at least one combinational element; identifying critical paths in the initial layout; forming a median line between the input and the output for at least one of the critical paths; and moving a location of a combinational element in the at least one critical path from a first location to a second location to form a revised layout, the first location being further from the median line than the second location.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lakshmi N. Reddy, Sourav Saha
  • Patent number: 8966426
    Abstract: A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Heng Kai Liu, Hui Yu Lee, Ya Yun Liu, Yi-Ting Lin
  • Patent number: 8959470
    Abstract: A method that determines the maximum number of logic cells that can be placed in a predetermined area on the base of an integrated circuit, and meet a voltage drop requirement. The method iteratively changes the logic cell spacing until the voltage drop requirement is made. This is done prior to the placement and extraction design phases as was done in previous methods. The predetermined area may be extrapolated across the base of the integrated circuit and meet the voltage drop requirements without the need to change the power grid, or to redo the placement and extraction phases. An integrated circuit designed according to the method, and an integrated circuit design system for using the method is also disclosed.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: February 17, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Shibashish Patel
  • Publication number: 20150046893
    Abstract: A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.
    Type: Application
    Filed: April 30, 2014
    Publication date: February 12, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: ERTUGRUL DEMIRCAN, MEHUL D. SCHROFF
  • Patent number: 8943455
    Abstract: Methods for standard cells using finFET standard cell structures with polysilicon on OD edges. Standard cells are defined using finFET transistors and having gate structures forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed on the edges of the active areas or OD areas of the standard cells. In a design flow, a pre-layout netlist schematic for the standard cells includes a three terminal MOS device corresponding to the polysilicon dummy structure on the edges of the standard cell. After an automated place and route process forms a device layout using the standard cells, a post layout netlist is extracted. Where two standard cells abut one another, a single polysilicon dummy structure is formed on the common boundary. A layout versus schematic comparison is then performed comparing the pre-layout netlist and the post-layout netlist to verify the layout obtained. Additional methods are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Hsin Chen, Kai-Ming Liu
  • Patent number: 8935642
    Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
    Type: Grant
    Filed: December 15, 2012
    Date of Patent: January 13, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vivek Bhardwaj, Oleg Levitsky, Dinesh Gupta
  • Patent number: 8930875
    Abstract: Embodiments of present invention include a method and apparatus of estimating power supply of a 3D IC. The method particularly includes obtaining current information and layout information of circuit modules contained in a specific region of the 3D IC, gridding the specific region so as to form at least one three-dimensional grid having a plurality of side edges along chip stacking direction of the 3D IC, determining current of at least one of the plurality of side edges based on the current information and layout information of the circuit modules, and estimating power supply of the 3D IC based on the current of the at least one side edge. With the method and apparatus embodiments of the invention, power supply of a 3D IC may be effectively estimated and analyzed.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventor: Wen Yin
  • Patent number: 8930866
    Abstract: A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Cheng Sung, Yue-Der Chih, Chia-Hsing Chen