Physical Design Processing Patents (Class 716/110)
  • Patent number: 10318676
    Abstract: Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: June 11, 2019
    Assignee: AMPERE COMPUTING LLC
    Inventors: Alfred Yeung, Subbayyan Venkatsan, Hamid Partovi, Vamsi Srikantam
  • Patent number: 10311195
    Abstract: A computer-implemented method for validating a design characterized by a multi-patterning layer is presented. The method includes receiving the multi-patterning layer in a memory of the computer when the computer is invoked to validate the design. The method further includes correcting, using the computer, a first error in a first shape of the multi-patterning layer in accordance with a first rule thereby forming a corrected layer. The method further includes incrementally validating, using the computer, a first portion of the corrected layer in accordance with the first error and a first connected component of a first graph associated with the multi-patterning layer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 4, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Yuli Xue, Weiping Fang, John Robert Studders, Byungwook Kim
  • Patent number: 10311200
    Abstract: Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 4, 2019
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Karim El Sayed, Terry Sylvan Kam-Chiu Ma, Xi-Wei Lin, Qiang Lu
  • Patent number: 10289777
    Abstract: A method comprises constructing thermal block representations of one or more circuit components or one or more sub-components of the one or more circuit components in an integrated circuit based, at least in part, on defined component parameters. The component parameters describe the one or more sub-components of the one or more circuit components. The thermal block representations have at least one simulation node. The method also comprises supplying a current using at least one current source or voltage controlled current source in a performance simulation. The current is supplied to a thermal path between a first simulation node and a second simulation node. The method further comprises determining a temperature distribution between the first simulation node and the second simulation node based on the current, a first determined voltage at the first simulation node, and a second determined voltage at the second simulation node.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sa-Lly Liu, Szu-Lin Liu, Jaw-Juinn Horng, Fu-Lung Hsueh
  • Patent number: 10217732
    Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Rany T. Elsayed, Niti Goel, Silvio E. Bou-Ghazale, Randy J. Aksamit
  • Patent number: 10216883
    Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Young Kim, Sung-We Cho, Tae-Joong Song
  • Patent number: 10204205
    Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
  • Patent number: 10192814
    Abstract: An electronics assembly includes a cooling chip structure having a device facing surface opposite a base surface and one or more sidewalls extending around a perimeter of the cooling chip structure between the device facing surface and the base surface. A plurality of fluid microchannels fluidly are coupled to a fluid inlet port and a fluid outlet port. A through substrate via extends from the base surface of the cooling chip structure to the device facing surface of the cooling chip structure, where the through substrate via intersects two or more fluid microchannels of the plurality of fluid microchannels.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: January 29, 2019
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Yuji Fukuoka, Ercan Dede, Kyosuke Miyagi
  • Patent number: 10185797
    Abstract: Electronic design automation systems and methods for extracting Microelectromechanical systems (MEMS) objects from a manufacturing MEMS layout are described for MEMS layouts directed to MEMS devices including mass and spring objects. Pattern recognition is used on a MEMS layer of the MEMS layout to identify beams and supports. The identified beams and supports are then used to derive a set of intermediate MEMS objects. The intermediate MEMS objects are used to derive a set of output objects, where the set of output objects includes at least two mass objects and at least one active spring object. The set of output objects may then be used to generate a Lagrangian model of the MEMS device described by the MEMS layout.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: January 22, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Janez Jaklic
  • Patent number: 10140411
    Abstract: A method for designing a system to be implemented on a target device, the method including generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing a corresponding net in the bounding box. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 27, 2018
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Jordan Swartz, Vadim Gouterman
  • Patent number: 10133842
    Abstract: Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active views. The electronic design is then associated with the set of active views that is stored in a data structure in a non-transitory computer accessible storage medium.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pawan Kulshreshtha, Amit Dhuria, Krishna Prasad Belkhale, Saulius Kersulis
  • Patent number: 10134090
    Abstract: A method, and associated system and computer program product, for configuring a network of interconnected sources and users of a commodity, the method comprises: providing a partition of the users into a plurality of disjoints parts; initializing a grouping of the sources and parts into a plurality of disjoint groups each one comprising one or more interconnected sources and parts; repeating selecting an enlarging group among the groups being over-supplied, selecting an adding part among the parts adjacent to the enlarging group being under-supplied, merging the adding part and the possible group thereof into the enlarging group, and updating the supply balance of the merged enlarging group and the residual demand of the parts thereof according to the merging until all the parts belong to a single group; and determining an arrangement of intercepting/regulating elements according to the conditions of the inter-part connections.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventor: Marcello Vitaletti
  • Patent number: 10102320
    Abstract: A predictive electronic circuit design system, method, and apparatus provide the ability to design an electronic circuit. An electronic computer aided design (CAD) environment server computing device is connected to the Internet and includes a machine learning module program. The machine learning module program has a netlist analyzer program, a database, and a classifier and predictor program. The netlist analyzer program receives a circuit netlist for a designed circuit from a user, characterizes the circuit netlist, and sends characterization data to the database. Characterization data from multiple users for multiple designed circuits are stored in the database. The classifier and predictor program uses design goal data, the characterization data for multiple designed circuits, and simulation results, to calculate and produce predictions and proposals for the user to make design changes to the designed circuit in order to better meet or exceed design goals.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: October 16, 2018
    Assignee: AUTODESK, INC.
    Inventor: Edward Sandor Pataky
  • Patent number: 9852251
    Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: December 26, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Hsiao-Tzu Lu, Duncan Robert McDonald, Chih-Wei Yuan, Wen-Lung Kang
  • Patent number: 9710580
    Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 18, 2017
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Teng-Nan Liao, Te-Hsun Fu, Hsin-Hsiung Liao, Cheng-Hong Tsai, Min-Hsiu Tsai
  • Patent number: 9690891
    Abstract: A method for facilitating semiconductor device manufacturing may include the following steps: receiving a custom design data set, which complies with a first element-identification scheme; generating a compatible design data set using the custom design data set, wherein data elements in the compatible design data set correspond to data elements in the custom design data set, and wherein the compatible design data set is compatible with a dummy-pattern-data generation module; generating a first dummy-pattern data set using the dummy-pattern-data generation module and the compatible design data set; and generating a second dummy-pattern data set using the first dummy-pattern data set, wherein data elements in the second dummy-pattern data set correspond to data elements in the first dummy-pattern data set, and wherein the second dummy-pattern data set complies with the first element-identification scheme.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: June 27, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Qiang Fan
  • Patent number: 9633159
    Abstract: Disclosed is an improved approach to implement timing signoff and optimization. Integrated MMMC timing closure functionality is provided in a single software session. The system provides the capability to perform signoff analysis, debugging, ECO, and TSO optimization for a large number of MMMC views in single software session.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 25, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vipul Parikh, Lalit Bharat, Shagufta Siddique, Prashant Sethia, Naresh Kumar
  • Patent number: 9626467
    Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Patent number: 9589085
    Abstract: A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths implicated in the check violations. Additional views combine views of different check types into unified summary tables. Embodiments create a second view to aggregate individual check violations that involve the same circuit objects over time, and output the second view. Output views are self-describing, to enable a single graphical user interface to operate across multiple simulator versions. Metadata tables describe data types presented in various view columns, and user interactions allowed therewith.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 7, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Keith Dennison, Vuk Borich
  • Patent number: 9496251
    Abstract: The present invention provides electrostatic discharge protectors. One aspect of the present invention provides an electrostatic discharge protector includes a substrate, an electrostatic discharge protection circuit disposed on the substrate, and a pickup ring surrounding the electrostatic discharge protection circuit. The pickup ring has a plurality of low resistance zones where a doping layer, a contact and a metal layer are connected in sequence, and the low resistance zones are distributed within the pickup ring separately and unequally.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 15, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Lu-An Chen, Mei-Ling Chao, Tien-Hao Tang
  • Patent number: 9483598
    Abstract: An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Sung Kyu Lim, Kambiz Samadi, Yang Du
  • Patent number: 9473113
    Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail, a collapsible power rail, multiple flip-flops, and power management circuitry. Each flip-flop of the multiple flip-flops includes a master portion that is coupled to the collapsible power rail and a slave portion that is coupled to the constant power rail. The power management circuitry is configured to combine a clock signal and a retention signal into a combined control signal and to provide the combined control signal to each flip-flop of the multiple flip-flops.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 18, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Harshat Pant, Ramaprasath Vilangudipitchai, Divjyot Bhan, Lipeng Cao, Sai Pradeep Kochuri, Parissa Najdesamii
  • Patent number: 9390213
    Abstract: Techniques generally disclosed herein relate to computation of a guard zone of a three-dimensional object. In some examples, guard zones may be computed by identifying intersection lines that couple adjacent planes of an object, and categorizing an external angle at an intersection line between adjacent planes as concave or convex. In some embodiments, for convex angles, a cylindrical surface can be determined that is located about an outside surface of the object and centered along the intersection line between the adjacent planes. In some embodiments, for concave angles, the external angle can be bisected with a bisection plane. A guard zone may be formed by one or more of (i) providing a guard zone plane parallel to the object that is a tangent to a given cylindrical surface, (ii) providing a guard zone plane parallel to the object that intersects a given bisection plane, and/or (iii) coupling adjacent guard zone planes.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: July 12, 2016
    Assignee: University of Calcutta
    Inventors: Rajat Kumar Pal, Ranjan Mehera
  • Patent number: 9355207
    Abstract: A method may include obtaining gate-level circuit design data that describes a gate-level circuit design. The gate-level circuit design data may include one or more instances of each of multiple cells that each may be associated with a corresponding default cell static timing data and a corresponding default cell stress data. The method may include selecting one of the instances of one of the multiple cells, determining in-design stress data associated with the selected instance, and determining whether the in-design stress data is not within a tolerance of the default cell stress data. In response to the in-design stress data not being within the tolerance of the default cell stress data, the method may include generating in-design static timing data describing a timing performance for the selected instance and updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 31, 2016
    Assignee: FUJITSU LIMITED
    Inventor: William W. Walker
  • Patent number: 9324451
    Abstract: A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: April 26, 2016
    Assignee: Broadcom Corporation
    Inventors: Saket Gupta, Yifei Zhang, Carl Monzel, Mark Jon Winter
  • Patent number: 9323883
    Abstract: A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Yao Chiang, Kuo-Hsun Huang, Chien-Hung Chen
  • Patent number: 9317645
    Abstract: Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer. The method further includes altering the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, and the second via further being in proximity to the first via. Further, the method includes further altering the initial circuit layout design by providing a subresolution assist feature in proximity to the second via.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventor: Ayman Hamouda
  • Patent number: 9209129
    Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: December 8, 2015
    Assignee: Synopsys, Inc.
    Inventors: Michael L. Rieger, Victor Moroz
  • Patent number: 9141733
    Abstract: Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined and the conductive region is divided into layers. Relative electric currents flowing along the current flow-through axis in each layer and along the current flow-in-and-terminate axis in each layer are evaluated to determine a total resistance value for the conductive region.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventor: Ning Lu
  • Patent number: 9041131
    Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung Hyuk Kang
  • Patent number: 9043741
    Abstract: A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: May 26, 2015
    Assignee: SYNOPSYS, INC.
    Inventors: Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma
  • Patent number: 9043740
    Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 26, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Kangho Lee, Xiaochun Zhu, Xia Li, Seung Hyuk Kang
  • Patent number: 9036365
    Abstract: A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: May 19, 2015
    Assignee: NEC Corporation
    Inventors: Manabu Kusumoto, Naoki Kobayashi, Noriaki Ando, Hiroshi Toyao
  • Patent number: 9038007
    Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: May 19, 2015
    Assignee: Altera Corporation
    Inventors: Peter Boyle, Iliya G. Zamek
  • Patent number: 9038011
    Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 19, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Shree Krishna Pandey, Changyu Sun
  • Publication number: 20150131368
    Abstract: A method and circuit for implementing sense amplifiers for sensing local write driver with bootstrap write assist for Static Random Access Memory (SRAM) arrays, and a design structure on which the subject circuit resides are provided. The circuit includes a sense amplifier used in both read and write operations with a write assist boost circuitry. The sense amplifier captures and amplifies write data at a selected SRAM cell column and drives the write data onto local bit lines. The write assist boost circuitry temporarily supplies an increased device voltage differential to the SRAM cell during write operations to significantly increase SRAM cell write ability.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chad A. Adams, Elizabeth L. Gerhard, Jeffrey M. Scherer
  • Patent number: 9032339
    Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 12, 2015
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Kevin M. Harer, Rajarshi Mukherjee, Mahantesh Narwade
  • Patent number: 9032355
    Abstract: A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: May 12, 2015
    Assignee: Helic S.A.
    Inventors: Sotirios Bantas, Konstantinos Karouzakis, Stefanos Stefanou, Apostolos Liapis, Labros Kokkalas
  • Publication number: 20150124907
    Abstract: Described herein is a fixed-point piece-wise linear (FP PWL) approximation technique for computations of nonlinear functions. The technique results in circuit designs having relatively few and simple arithmetic operations, short arithmetic operands and small-sized look-up tables and the circuits resultant there from can be efficiently pipelined to run at multi-GSamples/s throughputs. In one exemplary embodiment, the FP PWL approximation technique was used in the design of an energy-efficient high-throughput and high-precision signal component separator (SCS) for use with in an asymmetric-multilevel-outphasing (AMO) power amplifier. The FP PWL approximation technique is appropriate for use in any application requiring high-throughput, area and power constrained hardware implementations of nonlinear functions.
    Type: Application
    Filed: May 5, 2013
    Publication date: May 7, 2015
    Applicant: Massachusetts Institute of Technology
    Inventors: Yan Li, Zhipeng Li, Yehuda Avniel, Alexandre Megretski, Vladimir Marko Stojanovic
  • Publication number: 20150123655
    Abstract: A method of designing, for a magneto-resistive (MR) sensor, a protection circuit having a first and a second N-channel field-effect transistor (NFET) and at least one positive-negative (PN) diode is disclosed. The method may include determining a safe operating voltage range for the MR sensor and determining, within the safe operating voltage range, a normal operating voltage range for the MR sensor. The method may also include determining a protection threshold voltage range outside of the normal operating voltage range and within the safe operating voltage range of the MR sensor. The method may also include selecting device parameters to configure the first and second NFETs and the at least one PN diode to, in response to a voltage applied to the MR sensor being within a protection threshold voltage range, limit, by shunting current, the voltage applied to the MR sensor.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 7, 2015
    Inventors: Ephrem G. Gebreselasie, Icko E. T. Iben, Alain Loiseau, Andreas D. Stricker
  • Patent number: 9026973
    Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Chun Tien, Chen-Chi Wu, Kuo-Ji Chen
  • Patent number: 9009637
    Abstract: A method for making a matrix device including a matrix of photodetecting or photoemitting elements, the method including designing operations for: a) identifying, from at least one topology of the matrix device, one or more spurious conducting closed circuits; b) selecting at least one photodetecting or photoemitting element of the matrix device belonging to at least one of the spurious conducting closed circuits identified, the at least one element selected being made inactive.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 14, 2015
    Assignees: Commissariat á l'énergie atomique et aux énergies alternatives, ISORG
    Inventors: Christophe Premont, Romain Gwoziecki
  • Patent number: 9009646
    Abstract: A method for routing a design may comprise receiving a design for implementing in a target device, wherein the design includes an input/output (I/O) signal of a functional block, and wherein the functional block is assigned to a physical component of the target device; based on the design and on a routing resource graph representing the target device, calculating a route including the physical component and a physical pin of the target device; and assigning the physical pin of the target device to the I/O signal based on the calculated route.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Haneef Mohammed, Kyle Kearney
  • Publication number: 20150100934
    Abstract: A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: HELIC S.A
    Inventors: SOTIRIOS BANTAS, KONSTANTINOS KAROUZAKIS, STEFANOS STEFANOU, APOSTOLOS LIAPIS, LABROS KOKKALAS
  • Patent number: 9003341
    Abstract: A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Mei-Li Yu, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 9003345
    Abstract: A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector value is calculated based, at least in part, on a plurality of criteria vectors of the benchmark circuits. A shift is applied on each of the groups by the tuning vector value and a technology file, such as a 2.5 dimensional RC techfile, is regenerated.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Fan Wu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 9003344
    Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 7, 2015
    Assignee: Synopsys, Inc.
    Inventors: Christopher Kennedy, Changge Qiao
  • Patent number: 8990744
    Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Gerhard Metzger-Brückl, Rainer Leuschner
  • Patent number: 8987828
    Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 24, 2015
    Assignee: Synopsys, Inc.
    Inventors: Victor Moroz, Deepak D. Sherlekar
  • Patent number: 8977995
    Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: March 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sumit Arora, Oleg Levitsky, Amit Kumar, Sushobhit Singh