Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.

Abstract: In an aspect of the present disclosure is a system for simulating an electrical vertical takeoff and landing (eVTOL) aircraft, including a fuselage comprising one or more pilot inputs, each of the pilot inputs configured to detect pilot datum; a concave screen facing the fuselage; a plurality of projectors directed at the concave screen; a computing device communicatively connected to the plurality of projectors, the computing device configured to: receive the pilot datum detected by the pilot inputs; generate a simulated eVTOL flight maneuver as a function of the pilot datum; and command the plurality of projectors to display one or more images based on the simulated flight maneuver.

Abstract: Semiconductor modules are used for controlling drive motors such as the electric motors of electric vehicles. IGBT modules are one type of such semiconductor modules. During operation, heat losses arise in the power transistors and the diodes of the semiconductor modules, which causes an increase in their temperature. Therefore, the manufacturers of the IGBT modules recommend that the software of a control unit that controls an IGBT module be provided with a protective function which continuously monitors the temperature of the IGBT module and intervenes as necessary if an unacceptable temperature of a component of the IGBT module is reached. A temperature model is used for the calculation. The manufacturers provide a more accurate higher-order temperature model that however causes an increased amount of computation. According to the proposal, a reduced temperature model is used that is calculated using the balanced truncation method and is optimized for certain working ranges.

Abstract: A method for identifying design rule checking (DRC) violation types within an integrated circuit (IC) chip design includes receiving an IC chip design layout, and performing a DRC process on the IC chip design layout to identify DRC violations. Further, the method includes generating clustered heatmaps from heatmaps generated from the DRC violations. The method further includes identifying a first DRC violation type and a corresponding first cell pair within the IC chip design layout by analyzing the clustered heatmaps with a diagnostic model.

Abstract: An apparatus and method for designing memory macro blocks. A memory includes one or more memory banks, each with one or more arrays and input/output (I/O) blocks used to perform read accesses and write accesses. An array that utilizes multiple memory bit cells, and the I/O blocks are placed in a manner that they are abutting one another. The layout of the memory bit cells and the I/O blocks use a same subset of parameters of a semiconductor fabrication process. As a result, the memory bank does not include the placement of any boundary cells, which are used to improve yield of semiconductor layout. By skipping the use of the boundary cells, the dimensions of the memory bank are reduced, and layout density increases. Additionally, the memory bit cells use one or more p-type devices for one or more read pass gates.

Abstract: Embodiments of the present application provide a method and an apparatus for adjusting metal wiring density. By detecting metal wiring density in each of metal density detection windows in a target layout, a region in which the metal wiring density is greater than a preset density threshold can be quickly positioned in the target layout, thereby improving the layout correction efficiency; then a power fill mesh in a target metal density detection window in which the metal wiring density is greater than the preset density threshold is cropped multiple times, until the metal wiring density in each of the metal density detection windows is less than or equal to the preset density threshold, such that sufficient power fill meshes are retained in the target layout while the metal wiring density of the target layout is less than or equal to the preset density threshold.

Abstract: A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts.

Abstract: A method includes storing a base model generated using base data and receiving training data generated by compiling circuit designs. The method also includes generating, using the training data, a tuned model and generating, using the training data and the base data, a hybrid model. The method further includes receiving a selected cost function and biasing the base model, the tuned model, and the hybrid model using the selected cost function.

Abstract: The present disclosure provides a neural network computing-oriented modeling method and apparatus for distributed data routing. The method includes the following steps: S1, designing the distributed attribute of a physical tensor: abstracting a mapping relationship between a logic tensor and the physical tensor into three distributed attributes including a broadcast attribute, a scatter attribute and a local reduction attribute; S2, deducing the distributed attribute of an output tensor: specifying the distributed attribute of an input tensor, and then deducing the legal distributed attribute of the output tensor according to the known distributed attribute of the input tensor; and S3, judging, according to the distributed attribute situation, whether an intermediate communication primitive needs to be inserted to obtain the distributed attribute of a local physical tensor.

Abstract: A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.

Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.

Abstract: A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.

Abstract: An approach is disclosed herein for balancing layer densities in using an automated process. The approach disclosed herein operates on a region-by-region and layer-by-layer basis to perform parameterized layer balancing. In some embodiments, the process comprises determining densities of respective layers in respective regions, evaluating each layer and region to determine whether operations need to be taken to balance those layers in the corresponding regions, determining what those actions should be, and then implementing those actions. Additionally, in some embodiments, the process may operate in different orders and may be associated with a looping flow until a layout being processed has been balanced.

Abstract: A method for evaluating a heat sensitive structure involving identifying a heat sensitive structure in an integrated circuit design layout, the heat sensitive structure characterized by a nominal temperature, identifying a heat generating structure within a thermal coupling range of the heat sensitive structure, calculating an operating temperature of the first heat generating structure; calculating a temperature increase or the heat sensitive structure induced by thermal coupling to the heat generating structure at the operating temperature; and performing an electromigration (EM) analysis of the heat sensitive structure at an evaluation temperature obtained by adjusting the nominal temperature by the temperature increase induced by the heat generating structure.

Abstract: Model elements of an executable model, representing a physical system, are partitioned into one or more linear portions and one or more nonlinear portions. Simulating behavior of the physical system, by executing the model, includes, for each of multiple simulation time intervals, for a first nonlinear portion, computing a correlation matrix characterizing noise associated with one or more ports of the model. A scattering matrix corresponds to a portion of the physical system represented by the first nonlinear portion without accounting for any noise within the portion of the physical system. The correlation matrix is derived from the scattering matrix based on noise within the portion of the physical system. Noise sources representing noise within the portion of the physical system are identified based on the correlation matrix. At least one characteristic of noise associated with each noise source is computed, and noise characteristics are output at selected ports.

Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

Abstract: An integrated circuit structure includes a first metal level comprising a first plurality of interconnect lines along a first direction. A cell is on at least the first metal level, the cell having a pin comprising more than two of the first plurality of interconnect lines. A second metal level comprising a second plurality of interconnect lines overlays the first metal level, where the second plurality of interconnect lines is along a second direction. Two or more vias are on at least one of the second plurality of interconnect lines to connect to the pin.

Abstract: According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein.

Abstract: Methods and systems are described that improve simulations which use thermal models to test dynamic thermal mitigation of devices, such as smartphones. These methods and systems can use a thermal Reduced Order Model (ROM) that is trained through machine learning to provide efficient systems that can significantly reduce the time and computational resources required to build a simulation of a device's thermal behavior. The thermal model can be used in different usage scenarios with different power management and thermal management controls to test the device's thermal behavior.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: An apparatus for treating a substrate is disclosed. The apparatus for treating the substrate includes a housing having a treatment space inside the housing, a plate to support the substrate inside the housing, a heating member provided inside the plate to heat the substrate and including a plurality of heating zones, a temperature measuring member to measure a temperature of the substrate with respect to each of the plurality of heating zones of the heating member, and a control unit to control a temperature for the heating member in a dynamic section of a temperature change graph measured in the temperature measuring member. The control unit performs temperature control with respect to each of the plurality of heating zones of the heating member to uniformize the thickness of the thin film on the substrate.

Abstract: Embodiments of techniques for inverse design of physical devices are described herein, in the context of generating designs for photonic integrated circuits (including a multi-channel photonic demultiplexer). In some embodiments, an initial design of the physical device is received, and a plurality of sets of operating conditions for fabrication of the physical device are determined. In some embodiments, the performance of the physical device as fabricated under the sets of operating conditions is simulated, and a total performance loss value is backpropagated to determine a gradient to be used to update the initial design. In some embodiments, instead of simulating fabrication of the physical device under the sets of operating conditions, a robustness loss is determined and combined with the performance loss to determine the gradient.

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell in the first circuit; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.

Abstract: A system performs a layout design of a circuit for a small area satisfying a design rule within a short period of time. In a layout design system which includes a processing portion and in which a circuit diagram and layout design information are input to the processing portion, the processing portion has a function of generating layout data from the circuit diagram and the layout design information by performing a Q learning, the processing portion has a function of outputting the layout data, the processing portion includes a first neural network, and the first neural network estimates an action value function in the Q learning.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the register retiming of registers in the system driven by a different clock.

Abstract: A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

Abstract: Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wn and a height Hn are estimated for each volume element n in the conducting structure. Furthermore, the local resistivity ?n for each volume element n is estimated based on a function that is dependent upon the length L of the conducting structure and the width Wn and height Hn of the volume element n. The resistance of a conducting structure is estimated in dependence upon the resistivity ?n for each of the volume elements n in the plurality of volume elements in the conducting structure.

Abstract: Various techniques implement an electronic design with physical simulations using layout artwork. The approximate behaviors of the electronic design are determined. A region in the electronic design is identified. A first three-dimensional model is identified, if pre-existing, or generated, if non-existing, for the region in the electronic design. The behaviors of the region is determined using at least physics-based techniques or methodologies that are preconditioned upon at least a portion of the approximate behaviors determined for the electronic design.

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.

Abstract: A method for designing a narrowband acoustic wave microwave filter including: generating a modeled filter circuit design having circuit elements including an acoustic resonant element defined by an electrical circuit model that includes a parallel static branch, a parallel motional branch, and one or both of a parallel Bragg Band branch that models an upper Bragg Band discontinuity and a parallel bulk mode function that models an acoustic bulk mode loss; and generating a final circuit design. Generating the final circuit design includes optimizing the modeled filter circuit design to generate an optimized filter circuit design; comparing a frequency response of the optimized filter circuit design to requirements; selecting the optimized filter circuit design for construction into the actual acoustic microwave filter based on the comparison; and transforming the optimized filter circuit design to a design description file for input to a construction process.

Abstract: A semiconductor integrated circuit device having a power supply strap formed in a layer above a power supply line which supplies power to standard cells, a switch cell provided for the power supply line, the switch cell being capable of switching between electrical connection and disconnection between the power supply line and the power supply strap, and a sub-power supply strap connected to at least two power supply lines including the power supply line provided with the switch cell.

Abstract: A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim circuit sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.

Abstract: A graph-based analysis (GBA) output is obtained comprising timing information pertaining to a plurality of paths in an integrated circuit. A path-based analysis (PBA) is performed on the GBA output to analyze timing of the plurality of paths and generate a set of improved timing results; wherein the physical measurements used by the PBA are more accurate than the physical measurements used by the GBA. The PBA result is output to an optimizer to automatically adjust the circuit.

Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes flagging violations in response to a determination that the decomposed conflict graph is not colorable.

Abstract: A method for performing a rewind functional verification includes identifying state variables that model a number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and a direction of a register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the retimed design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.

Abstract: Adaptive power regulation methods and systems are disclosed. In one aspect, one or more process sensors for memory elements are provided, which report information relating to inherent speed characteristics of sub-elements within the memory elements. Based on this reported information, a controller ascertains an appropriate power level to insure a proper data retention voltage (DRV) is applied on voltage rails by a power management unit (PMU) circuit. By using the proper DRV based on the speed characteristics of the sub-elements within the memory elements, power conservation is achieved.

Abstract: Systems and methods can be used to detect thermal anomalies in a target scene of an infrared image. Acquired thermal image data can be compared to a statistical thermal profile to detect thermal anomalies in the image data. Anomaly data based on the comparison can be used to generate an image representing locations and/or severity of detected anomalies. Systems can be used to acquire thermal image data for generating and/or updating statistical thermal profiles for use in anomaly detection processes. Auxiliary measurement devices can provide measurement data representative of one or more parameters of the target scene. The measurement data can be used to select from a plurality of possible statistical thermal profiles associated with the target scene to best match the current parameters of the scene.

Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.

Abstract: Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.

Abstract: A computer-implemented method for validating a design characterized by a multi-patterning layer is presented. The method includes receiving the multi-patterning layer in a memory of the computer when the computer is invoked to validate the design. The method further includes correcting, using the computer, a first error in a first shape of the multi-patterning layer in accordance with a first rule thereby forming a corrected layer. The method further includes incrementally validating, using the computer, a first portion of the corrected layer in accordance with the first error and a first connected component of a first graph associated with the multi-patterning layer.

Abstract: Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

Abstract: A method comprises constructing thermal block representations of one or more circuit components or one or more sub-components of the one or more circuit components in an integrated circuit based, at least in part, on defined component parameters. The component parameters describe the one or more sub-components of the one or more circuit components. The thermal block representations have at least one simulation node. The method also comprises supplying a current using at least one current source or voltage controlled current source in a performance simulation. The current is supplied to a thermal path between a first simulation node and a second simulation node. The method further comprises determining a temperature distribution between the first simulation node and the second simulation node based on the current, a first determined voltage at the first simulation node, and a second determined voltage at the second simulation node.

Abstract: Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.

Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.

Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.