Abstract: Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract: One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value.

Abstract: A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement.

Abstract: A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.

Abstract: Circuit placement for increasing circuit packing density for an integrated circuit is described. A design is synthesized and mapped. Components of the design are placed to provide a first placed design. A congestion density map is generated for the first placed design. A congestion region in the congestion density map is identified and targeted for determining if the first placed design has a control set conflict. A first circuit object associated with the control set conflict is selected and either re-placed or re-synthesized to at least diminish the control set conflict.

Abstract: A method of designing a layout of a semiconductor integrated circuit having a hard macro includes acquiring a condition for permitting wirings with respect to a given region within the hard macro, and searching a passing wiring that passes through the given region among the wirings that are arranged on the semiconductor integrated circuit. The method further includes allowing a normal passing wiring that satisfies the condition to pass through the hard macro, and wiring a defaulting passing wiring that does not satisfy the condition so as to bypass the hard macro among the searched passing wirings.

Abstract: Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern.

Abstract: Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.

Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor.

Abstract: A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.

Abstract: A layout method is provided, adaptable to place cell on a chip. Firstly, a chip area is assigned for a floor plan. A global reservation deployment process is then performed to define a plurality of room units to be uniformly distributed on the chip area. Cells are placed on the chip based on the floor plan. The chip area is categorized into at least a high frequency region and a low frequency region according to operation frequencies of the placed cells thereon. A frequency based reservation deployment process is then performed to move one or more room units distributed in the low frequency region toward the high frequency region. A local cell replacement process, a routing and timing analysis are performed. If hotspots are induced, room units around the hotspots are redistributed, and then the steps of local cell replacement, routing and timing analysis are repeated.

Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.

Abstract: A number of virtual regionalization lines are laid out across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip. One of the plurality of regions on the chip is designated as a master region and each of a remainder of the plurality of regions on the chip is designated as a duplicate region. A number of functional blocks are placed in the master region. Each of the functional blocks is replicated in each duplicate region by placing each functional block in each duplicate region so as to be symmetric with the corresponding functional block in the master region about the virtual regionalization lines. Wires are routed in the master region. The wires routed in the master region are replicated in each duplicate region so as to be symmetric about the virtual regionalization lines.

Abstract: In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N<M, is set as a gravity point to attract an input of the (N+1)th 2-pin logic cell, thereby optionally flipping the (N+1)th 2-pin logic cell.

Abstract: A method of area compaction for integrated circuit layout design comprises determining physical extent boundaries for each layer of at least first circuit and second circuit building blocks. Determining physical extent boundaries includes determining for each respective layer of the first circuit and second circuit building blocks (i) a used portion and (ii) a free portion. The used portion corresponds to a functional portion of the respective circuit building block and the free portion corresponds to a non-functional portion of the respective circuit building block. The method further includes establishing packing keys with respect to the determined physical extent boundaries of each layer of the first circuit and second circuit building blocks, respectively. The packing keys define an interlocking characteristic for packing compaction of the corresponding first circuit or second circuit building block with another circuit building block.

Abstract: A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).

Abstract: A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device and an on-chip spiral inductor device, interpreting data obtained from the recognizing the passive device, breaking the passive device into a plurality of sections, the plurality of sections including a terminal of a model call, extracting parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction, connecting the terminal to a pre-layout passive network by selectively low and high resistive paths set by the parameters of the passive device depending on whether crossing lines are present or not present in one of the plurality of sections, connecting the terminal to a distributed passive model, and coupling the crossing lines to the terminal via capacitors produced in an extracted netlist with the passive device havin