Plds Patents (Class 716/128)
  • Patent number: 10783308
    Abstract: A graphical tool for a design of a substrate of an integrated circuit device is described. The graphical tool comprises a processor configured to: display locations of probes for a first plurality of contact elements associated with the substrate; display locations of BGA contact elements associated with the substrate; identify interconnect elements between the first plurality of contact elements and the BGA contact elements; and display connections lines representing the identified interconnect elements. A method of designing a substrate of an integrated circuit device is also described.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 22, 2020
    Assignee: XILINIX, INC.
    Inventors: Lik Huay Lim, Andy Widjaja, King Yon Lew, Xuejing Che, Mohsen H. Mardi
  • Patent number: 10664561
    Abstract: Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 26, 2020
    Assignee: Xilinx, Inc.
    Inventors: Pradip K. Kar, Satyaprakash Pareek, Shangzhi Sun, Bing Tian
  • Patent number: 10571954
    Abstract: Examples herein disclose an identification of a set of skew requirements corresponding to a set of data signals. Based on the set of skew requirements, the examples prioritize an order of transmission for the set of data signals. The example queue the set of data signals in accordance with the prioritized order.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 25, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: David Maciorowski, Christopher Kroeger
  • Patent number: 10564970
    Abstract: A processing system comprising multiple tiles and an interconnect between the tiles. The interconnect is used to communicate between a group of some or all of the tiles according to a bulk synchronous parallel scheme, whereby each tile in the group performs an on-tile compute phase followed by an inter-tile exchange phase with the exchange phase being held back until all tiles in the group have completed the compute phase. Each tile in the group has a local exit state upon completion of the compute phase. The instruction set comprises a synchronization instruction for execution by each tile upon completion of its compute phase to signal a sync request to logic in the interconnect. In response to receiving the sync request from all the tiles in the group, the logic releases the next exchange phase and also makes available an aggregated a state of all the tiles in the group.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 18, 2020
    Assignee: Graphcore Limited
    Inventors: Simon Christian Knowles, Alan Graham Alexander
  • Patent number: 10558777
    Abstract: A method of implementing a partial reconfiguration in an integrated circuit device is described. The method comprises reading a netlist for a design of a circuit comprising a reconfigurable module; defining a first region of the integrated circuit device having the reconfigurable module; defining a second region that encompasses the first region; placing the reconfigurable module of the design in the first region, wherein the reconfigurable module comprises a partition pin of a plurality of available partition pins; selectively removing the partition pin; routing drivers and loads that are in the second region; and generating a partial bitstream for the reconfigurable module.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 11, 2020
    Assignee: Xilinx, Inc.
    Inventors: Hao Yu, Raymond Kong
  • Patent number: 10318693
    Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Zhuo Li, Charles Jay Alpert, William Robert Reece, Thomas Andrew Newton
  • Patent number: 9760669
    Abstract: A method, computer program product, and system for rerouting wires based on wire size and spacing requirements including partitioning a chip into a plurality of global routing tiles, assigning a set of wires to one or more of the plurality of global routing tiles, sorting the set of wires into one or more groups based on line spacing requirements for wires of the set of wires, each of the one or more groups includes one or more wires with a common line spacing requirement, and organizing the one or more groups in a numeric order based on the common line spacing requirement of each group.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Markus Buehler, Diwesh Pandey, Sven Peyer
  • Patent number: 9099195
    Abstract: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 4, 2015
    Assignee: The Trustees of Princeton University
    Inventors: Wei Zhang, Niraj K. Jha, Li Shang
  • Patent number: 9009646
    Abstract: A method for routing a design may comprise receiving a design for implementing in a target device, wherein the design includes an input/output (I/O) signal of a functional block, and wherein the functional block is assigned to a physical component of the target device; based on the design and on a routing resource graph representing the target device, calculating a route including the physical component and a physical pin of the target device; and assigning the physical pin of the target device to the I/O signal based on the calculated route.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Haneef Mohammed, Kyle Kearney
  • Patent number: 8990757
    Abstract: An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 24, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: King W. Chan, William C. T. Shu, Sinan Kaptanoglu, Chi Fung Cheng
  • Patent number: 8959469
    Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Altera Corporation
    Inventors: Doris Tzu-Lang Chen, Deshanand Singh
  • Publication number: 20150046895
    Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventor: Venkat Konda
  • Patent number: 8949763
    Abstract: A system for computer-aided design (CAD) of an integrated circuit (IC) uses a computer. The computer is configured to optimize placement, routing, and/or region configuration of the integrated circuit (IC) by maximizing a number of low-power regions in the integrated circuit (IC).
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 3, 2015
    Assignee: Altera Corporation
    Inventor: Ryan Fung
  • Patent number: 8930872
    Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Netronome Systems, Incorporated
    Inventor: Gavin J. Stark
  • Patent number: 8914762
    Abstract: A method, computer-readable medium and apparatus for creating a platform-specific logic design from an input design are disclosed. For example, a method includes receiving an input design and an identification of a target device. The method next determines an unconnected external interface of the input design and detects an unconnected external interface of the target device. The method then generates an updated design from the input design. The updated design includes the input design and further includes a connection between the unconnected external interface of the input design and the unconnected external interface of the target device.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: December 16, 2014
    Assignee: Xilinx, Inc.
    Inventors: Martin Sinclair, Brian Cotter
  • Patent number: 8904333
    Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Haifeng Bai, Yin Guo, Xuewen He, Kun Wu, Lei Zhang, Shayan Zhang
  • Publication number: 20140351782
    Abstract: The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.
    Type: Application
    Filed: June 2, 2014
    Publication date: November 27, 2014
    Applicant: Element CXI, LLC
    Inventor: Steven Hennick Kelem
  • Patent number: 8881085
    Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: November 4, 2014
    Assignee: Xilinx, Inc.
    Inventors: James Karp, Greg W. Starr, Mohammed Fakhruddin
  • Patent number: 8881082
    Abstract: A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace, within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity; and output a new logic gate design based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, producing a same output as the application specific integrated circuit with the logic gate design, based on same inputs.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Infinera Corporation
    Inventor: Vinay Adavani
  • Patent number: 8875080
    Abstract: A design methodology is provided to fully automate the creation of multiple-personality programmable macros for use in metal/via programmable ICs. Programmability is achieved using programmable switches, each of which may include one or more metal traces and/or vias on one or more layers configured in series, in parallel, or in combination. Multiple overlapping switches may exist in the same location. That is, switches may be defined that use some of the same resources. Any one of the switches may be “turned on,” while the remaining switches remain turned off. As part of the design methodology, different nets or parts of an electrical circuit design are programmed by replacing the switches with hard connections that close the circuit, or with no connections so as to open the circuit, or cause the circuit to remain open. The methodology allows for sharing routing or programming resources to achieve optimize layout area usage.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Baysand Inc.
    Inventors: Jonathan C Parks, Yin Hao Liew, Jeremy Lee Jia Jian
  • Patent number: 8875073
    Abstract: A method relating generally to computer aided design is disclosed. In such method, a block-based model of a hardware realizable system is obtained. An internal gateway-in and an internal gateway-out of a module of the block-based model are identified. An interface protocol is assigned for the internal gateway-in and the internal gateway-out. Data type and data propagation for the module at the internal gateway-in and the internal gateway-out are analyzed. The internal gateway-in and the gateway-out are transformed into an input/output interface. Integrated code is generated for subsequent realization of the input/output interface in hardware.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 28, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Jinsong Du
  • Patent number: 8863060
    Abstract: An Infrastructure Description Language (IDL) includes Service Level Hints (SLHs) and Service Level Requirements (SLRs). The SLHs and SLRs are used to configure at least one hardware resource in a computing system having an intelligent configurator to broker a hardware configuration based on the SLHs and SLRs.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Arun S. Jagatheesan, Zheng Li
  • Patent number: 8856714
    Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Sun Hwang, Sung-Hee Yun, Jae-Hoon Jeong, Won-Cheol Lee, Tae-Heon Lee, Young-Hoe Cheon
  • Patent number: 8856713
    Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: October 7, 2014
    Assignee: Altera Corporation
    Inventors: Ketan Padalia, Ryan Fung
  • Patent number: 8856718
    Abstract: A computer-implemented method of estimating signal congestion in routing resources of a programmable logic device (PLD), wherein the routing resources include configurable interface blocks (CIBs) and wires of different types supported by the CIBs. The method includes identifying, from a representation of a PLD stored within a computer system, components of the PLD to be connected in a configuration of the PLD. A CIB associated with an identified PLD component is then selected. A wire type supported by the selected CIB is also selected. The number of wires of the selected type needed at the selected CIB to implement the PLD configuration and the number of wires of the selected type provided by the CIB are calculated. Signal congestion at the selected CIB is estimated from at least the needed number of wires and the provided number of wires.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 7, 2014
    Assignee: Lattice Semiconductor Corporation
    Inventor: Jun Zhao
  • Patent number: 8819615
    Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 26, 2014
    Assignee: STMicroelectronics SA
    Inventors: Julien Le Coz, Sylvain Engels, Alain Tournier
  • Publication number: 20140237441
    Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
    Type: Application
    Filed: January 10, 2014
    Publication date: August 21, 2014
    Applicant: Altera Corporation
    Inventors: David Samuel Goldman, Mark Bourgeault, Vaughn Betz, Alan Louis Herrmann
  • Patent number: 8788996
    Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors. In one embodiment, manufacturing yields, compatibility characteristics, performance requirements, and system health (e.g., the number of components operating properly) are factored into changes to the operational characteristics of functional components. In one exemplary implementation, the changes to operational characteristics of a functional component are coordinated with changes to other functional components. Workflow scheduling and distribution is also adjusted based upon the changes to the operational characteristics of the functional components. For example, a functional component configuration controller changes the operational characteristics settings and provides an indication to a workflow distribution component.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 22, 2014
    Assignee: Nvidia Corporation
    Inventors: Michael B. Diamond, John S. Montrym, James M. Van Dyke, Michael B. Nagy, Sean J. Treichler
  • Patent number: 8789001
    Abstract: A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 22, 2014
    Assignee: Tabula, Inc.
    Inventors: Eric A. Sather, Steven Teig
  • Patent number: 8769463
    Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Nvidia Corporation
    Inventors: Clay Berry, Timothy J. McDonald
  • Patent number: 8756548
    Abstract: A method for operating a computing system includes: receiving an application-tree for instantiating an application in a reconfigurable hardware device; operating a kernel unit for determining an unoccupied logic-sector within a reconfigurable hardware device; calculating a layout section from the application-tree according to the unoccupied logic-sector for instantiating a fragment circuitry corresponding to the layout section; and determining a system table for connecting the fragment circuitry to other portions of the application to form the application having the fragment circuitry.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: June 17, 2014
    Assignee: Xcelemor, Inc.
    Inventor: Peter J Zievers
  • Patent number: 8751993
    Abstract: A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: June 10, 2014
    Assignee: Resonant LLC
    Inventors: Neal Fenzi, Kurt Raihn
  • Patent number: 8751989
    Abstract: A technique for routing signal traces in an electronic package design includes extracting near-end and far-end crosstalk values for traces and vias from a model of the electronic package design. The extracted values are then length-normalized and the normalized values are allocated to coupling factors of a cost-function. A first bus routing for the electronic package design is performed to provide a first routed design. Length segments from the first routed design are extracted and inserted in the cost-function. Crosstalk for each bus net is accumulated using the cost-function. In response to the accumulated crosstalk being less than a determined limit, the first routed design is saved. In response to the accumulated crosstalk being greater than the determined limit, an additional bus routing for the electronic package design is performed.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hubert Harrer, Philip Scott Honsinger, Andreas Huber, Dierk Kaller, Martin Kindscher
  • Patent number: 8751997
    Abstract: Up-binning a circuit design includes receiving a first bitstream specifying the circuit design. The circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit. Using a processor, a first parameter of the first bitstream is determined. The first parameter is applied to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design. A timing analysis is performed upon the parameterized hardware netlist. The process further includes determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit. The second speed grade is slower than the first speed grade.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 10, 2014
    Assignee: Xilinx, Inc.
    Inventor: Amit Gupta
  • Patent number: 8745566
    Abstract: A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 3, 2014
    Assignee: Altera Corporation
    Inventors: Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Patent number: 8739101
    Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 27, 2014
    Assignee: Maxeler Technologies Ltd.
    Inventor: Robert Gwilym Dimond
  • Patent number: 8732646
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: May 20, 2014
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron R. McClintock, Brian D. Johnson, Richard G. Cliff, Srinivas T. Reddy, Christopher F. Lane, Paul Leventis, Vaughn Betz, David Lewis
  • Patent number: 8709684
    Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang, Fu-Lung Hsueh
  • Patent number: 8701069
    Abstract: A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, functional objects, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The functional objects are grouped based upon having a cycle position dependent upon common factors. Common control logic elements are allocated to groups of functional objects. The graph and allocated control logic is used to define a hardware design for the pipelined parallel stream processor.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 15, 2014
    Assignee: Maxeler Technologies, Ltd.
    Inventor: Robert Gwilym Dimond
  • Publication number: 20140089885
    Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 27, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Julien Le Coz, Sylvain Engels, Alain Tournier
  • Patent number: 8683412
    Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Miles P. McGowan
  • Patent number: 8683410
    Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. For at least a first set of operations that has a start operation and an end operation, the method assigns a particular operation in the first set to a first operational cycle based at least partially on the position of the particular operation with respect to the start and end operations.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 25, 2014
    Assignee: Tabula, Inc.
    Inventors: Andre Rohe, Steven Teig
  • Patent number: 8677298
    Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify critical and near-critical cyclic logic paths within the user logic design, applying timing optimizations to the critical and near-critical cyclic logic paths, and retiming logic paths other than the critical and near-critical cyclic logic paths.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: March 18, 2014
    Assignee: Altera Corporation
    Inventors: Valavan Manohararajah, David Lewis, David Galloway, Ryan Fung
  • Patent number: 8671377
    Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 11, 2014
    Assignee: Altera Corporation
    Inventors: David Samuel Goldman, Mark Bourgeault, Vaughn Betz, Alan Louis Herrmann
  • Patent number: 8671379
    Abstract: Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: March 11, 2014
    Assignee: Xilinx, Inc.
    Inventors: Jitu Jain, Vinay Verma, Taneem Ahmed, Sandor S. Kalman, Sanjeev Kwatra, Christopher H. Kingsley, Jason H. Anderson, Satyaki Das
  • Publication number: 20140047405
    Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 13, 2014
    Applicant: Altera Corporation
    Inventors: Terry Borer, Gabriel Quan, Stephen D. Brown, Deshanand P. Singh, Chris Sanford, Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Patent number: 8650525
    Abstract: Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: February 11, 2014
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 8645892
    Abstract: An integrated circuit (IC) design includes configurable circuits arranged in a mesh structure to facilitate routing of signals between different platforms or logic blocks within the design. Each configurable circuit has a semiconductor element with input and output terminals in a first semiconductor layer, input/output (I/O) ports corresponding to directions of the mesh structure in a second semiconductor layer, configurable input vias to allow a signal traveling in a first direction to be received, and configurable output vias that allow an output signal to be output from the configurable circuit in a second direction.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vishal Gupta, Puneet Dodeja, Hans Raj Singh
  • Patent number: 8645890
    Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: February 4, 2014
    Assignee: Tabula, Inc.
    Inventors: Andre Rohe, Steven Teig
  • Patent number: 8640071
    Abstract: A circuit design system 10 includes storage means 11 to store structure description information 11a of a reconfigurable circuit including an array of cells 1 including a plurality of switches 2, and application circuit netlist information 11b used to specify an application, circuit generation unit 12a to generate structure description information 11a based on the structure description information 11a and the application circuit netlist information 11b stored in the storage means 11, and circuit evaluation unit 12b to evaluate the structure description information 11a generated by the circuit generation unit 12a, wherein the circuit generation unit 12a generates the structure description information 11a by deleting at least one of the switches 2 from the structure description information 11a based on an evaluation result obtained by the circuit evaluation unit 12b.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: January 28, 2014
    Assignee: NEC Corporation
    Inventor: Shogo Nakaya