Routing Patents (Class 716/126)
  • Patent number: 11392749
    Abstract: A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, KuoPei Lu, Lester Chang, Ze-Ming Wu
  • Patent number: 11360789
    Abstract: Methods are provided for configuring a reconfigurable hardware device to execute a user application. Such a method includes providing static shell logic on the device. The static shell logic is controlled by a primary management core for managing operation of the device, and has a predetermined hardware interface. The method includes configuring on the device, via the primary management core, dynamic shell logic for implementing dynamically-selected shell functionality. The dynamic shell logic includes a secondary management core, adapted to communicate with the primary management core via the hardware interface, for managing operation of the dynamic shell logic. The method further comprises configuring on the device, via the primary management core, application logic, having an interface with the dynamic shell logic, for executing the user application. The secondary management core uploads to the primary management core dynamic code to adapt the primary management core for use with the dynamic shell logic.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: June 14, 2022
    Assignee: International Business Machines Corporation
    Inventors: Burkhard Ringlein, Francois Abel, Beat Eugen Weiss
  • Patent number: 11275881
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having one or more unoptimized nets. Embodiments may further include applying a genetic algorithm to the electronic design, wherein the genetic algorithm includes a multi-stage routing analysis. A first stage analysis may apply a device-level global routing analysis, a second stage analysis may include an intra-row routing analysis, a third stage may include an inter-row routing analysis, and a fourth stage may include a post-routing optimization analysis. Embodiments may also include generating an optimized routing of the one or more unoptimized nets and displaying the optimized routing at a graphical user interface.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 15, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Weifu Li, Elias Lee Fallon, Supriya Ananthram, Weiyi Qi, Sheng Qian
  • Patent number: 11250197
    Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Vinod Kumar Lakshmipathi, Venugopal Sanaka, Babu Suriamoorthy, Madan Krishnappa, Pavan Kumar Patibanda
  • Patent number: 11163925
    Abstract: A simulator models an energy and power system. The simulator allows a user to manipulate digital representations of nodes, which represent one or more components of power and energy assets. The simulator also allows a user to manipulate digital representations of edges, which connect the nodes, to form a power and energy network. A plurality of object classes correspond to the nodes and edges. The object classes comprise class inheritance structures so that constraints of a parent class are retained by one or more child classes. The interface on the simulator allows a user to model a power and energy system by allowing the user to connect the nodes with edges to construct a power and energy system, wherein the object classes for the nodes, when executed by the simulator, implement one or more dynamical models to model the power and energy assets.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: November 2, 2021
    Assignee: Enernet Global, LLC
    Inventor: Stephen Schneider
  • Patent number: 11163933
    Abstract: A method that includes operations below and at least one of the operations is performed by a processor. Whether at least one condition is present in a signal to be received or transmitted by a terminal of a cell of an integrated circuit is determined. When the at least one condition is present in the signal, a plurality of conductive segments of the integrated circuit is assigned, to transmit the signal to the terminal of the cell. Each conductive segment of a first set of conductive segments of the plurality of conductive segments has a first predetermined width, and a distance between adjacent two conductive segments of the first set of conductive segments is greater than the first predetermined width.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jack Liu
  • Patent number: 11151299
    Abstract: A system includes at least one Input/Output (I/O) interface and a processor. The processor is coupled to the at least one I/O interface. The processor is configured to perform, according to a file or a rule inputted from the at least one I/O interface, operations below. When the at least one condition is present in a signal to be received or transmitted by a terminal of a cell, a plurality of conductive segments is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. When the at least one condition one is not present in the signal, a single route is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. The single route and each of the conductive segments are configured to have the same width.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jack Liu
  • Patent number: 11138361
    Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Patent number: 11106632
    Abstract: An illustrative data storage management system relies on a specially configured proxy server to operate software containers on a proxy server, maintain resources needed by the software containers, and interwork with other system components. Illustratively, a catalog service on the proxy server maintains a software cache according to maintenance rules and also maintains an associated cache catalog. The software containers are generally managed and operated by an illustrative container manager also hosted by the proxy server. The illustrative software cache comprises contents needed by the software containers, such as pre-configured container templates, DBMS software components, lightervisors representing target operating systems, and storage management software for performing test and storage operations. The maintenance rules govern when cache contents should be purged and moved into offline archive copies.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 31, 2021
    Assignee: Commvault Systems, Inc.
    Inventors: Prashanth Nagabhushana Bangalore, Diptiman Basak, Girish Ramohalli Gopala Rao, Shankar Reddy Vullupala, Saamaja Vupputuri
  • Patent number: 11106842
    Abstract: Systems and methods for selecting equipment for use in buildings are disclosed. The system may include at least one processor configured to perform operations that include accessing a floor plan demarcating a plurality of rooms. The operations further include accessing functional requirements associated with the rooms and accessing technical specifications associated with the functional requirements. The operations include performing floor plan analysis on the floor plan to ascertain room features associated with the functional requirements and technical specifications. The operations include generatively analyzing the room features to determine a customized equipment configuration for at least some of the rooms, and generating a manufacturer dataset including a room identifier, an equipment identifier, and the customized equipment configuration. The manufacturer dataset enables a manufacturer to customize equipment for the rooms and package the customized equipment to display the room identifier.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 31, 2021
    Assignee: BEAMUP LTD.
    Inventors: Tom Segev, Stephane Levy, Guy Austern, Yonatan Goyhman
  • Patent number: 11087054
    Abstract: Systems and methods for generating wiring diagrams for equipment are disclosed. The system may include at least one processor configured to perform operations that may include accessing a floor plan defining a plurality of rooms, receiving input associating at least one of a plurality of functional requirements with at least one room of the plurality of rooms, and accessing, in a data structure, technical specifications associated with electrical equipment. Operations may include selecting, from the data structure, a plurality of the technical specifications, generatively analyzing the at least one room in conjunction with the functional requirement and the selected technical specifications in order to select a piece of equipment for the at least one room and select an equipment placement location, accessing structural data associated with the at least one room, and generating a wiring diagram for the at least one room using the selected technical specifications and the structural data.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 10, 2021
    Assignee: BEAMUP LTD.
    Inventors: Guy Austern, Tom Segev, Stephane Levy, Yonatan Goyhman
  • Patent number: 11030377
    Abstract: Various embodiments described herein provide for routing of wires of a network of a circuit design based on pin placement within a routing blockage. In particular, various embodiments provide a routing solution for a circuit design with zero blockage violation when there is no pin inside routing blockage of the circuit design, and uses a parameter (e.g., an adjustable parameter) that controls accuracy at which a routing process handles a pin (e.g., as placed by a placement stage) in routing blockage of the circuit design. For example, the parameter can control how much detour is acceptable when handling routing for a pin inside a routing blockage.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 8, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Mehmet Can Yildiz
  • Patent number: 11010236
    Abstract: Embodiments are directed towards the visualization of machine data received from computing clusters. Embodiments may enable improved analysis of computing cluster performance, error detection, troubleshooting, error prediction, or the like. Individual cluster nodes may generate machine data that includes information and data regarding the operation and status of the cluster node. The machine data is received from each cluster node for indexing by one or more indexing applications. The indexed machine data including the complete data set may be stored in one or more index stores. A visualization application enables a user to select one or more analysis lenses that may be used to generate visualizations of the machine data. The visualization application employs the analysis lens to produce visualizations of the computing cluster machine data.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 18, 2021
    Assignee: SPLUNK INC.
    Inventors: Cary Glen Noel, Kirubakaran Pakkirisamy, Alex Raitz, Pierre Tsai
  • Patent number: 10977421
    Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10963616
    Abstract: Embodiments disclosed herein describe systems, methods, and products for aligning wires in an integrated circuit (IC) design. An illustrative computer may identity multiple references in a first set of wires and multiple targets in a second set of wires in the IC design. The computer may determine reference target pairs from the multiple references and multiple targets. The computer may calculate a path difference for each of the reference target pairs and align the corresponding wires based upon the path difference while obeying minimum spacing rules. The computer may also allow a circuit designer to modify or override the computer selected references, targets, or reference target pairs. Embodiments disclosed herein therefore mitigate the alignment problems of shorting and incorrect spacing.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 30, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vidhi Bansal, Devendra Deshpande
  • Patent number: 10936773
    Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Daellenbach, Sven Peyer
  • Patent number: 10854291
    Abstract: Briefly, embodiments of claimed subject matter relate to backup of parameters, such as binary logic values, stored in nonvolatile memory, such as one or more SRAM cells. Binary logic values from a SRAM cell, for example, may be stored utilizing resistance states of a magnetic random-access memory (MRAM) element. Parameters stored in one or more MRAM elements may be restored to SRAM memory cells following a backup.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Akhilesh Ramlaut Jaiswal, Mudit Bhargava, George McNeil Lattimore
  • Patent number: 10827387
    Abstract: [Object] To make it possible to reduce a load on a controller configured to perform centralized control of a network. [Solution] There is provided an apparatus including: an acquisition unit configured to acquire traffic information relating to traffic of a cell group including two or more cells; and a provision unit configured to provide the traffic information for a control device, the control device being configured to perform routing control of traffic of a plurality of cell groups including the cell group.
    Type: Grant
    Filed: October 20, 2018
    Date of Patent: November 3, 2020
    Assignee: SONY CORPORATION
    Inventor: Shinichiro Tsuda
  • Patent number: 10817642
    Abstract: Various embodiments are directed to a mechanism for reserving power resources to address non-uniform and complex routings on a redistribution layer of a flip-chip. Reserving power resources may be performed by rerouting RDL nets by, for example, identifying an initial RDL net route for a RDL net; defining an outer boundary relative to the initial RDL net route, wherein a perimeter of the outer boundary is defined at a defined distance away from the initial RDL net route; defining one or more blockages extending from bumps to intersect the outer boundary; subdividing the initial RDL net route into a plurality of net portions, wherein each net portion is bounded by a portion of the outer boundary and one or more of the blockages; and rerouting at least one of the plurality of net portions to be adjacent at least one blockage bounding the circuit net portion.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 27, 2020
    Assignee: SYNOPSYS, INC.
    Inventor: Hsien-Shih Chiu
  • Patent number: 10796056
    Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory A. Northrop, Lionel Riviere-Cazaux, Lars Liebmann, Kai Sun, Norihito Nakamoto
  • Patent number: 10790223
    Abstract: An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 29, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Fan Yang, Yuan-Hung Lin, Yu-Cheng Sun, Steve S. A. Wan
  • Patent number: 10769825
    Abstract: A matched array technology system and method for displaying in a two-dimensional array the structured interaction between the expectations of manager and employee in an organization. Proxy values of employee and manager perspectives are defined and scaled so the axes of the array contain corresponding indicators resulting in a “matched array” and an embedded, unique “alignment vector” of the cells where employee and manager expectations are equivalent. The matched array display shows all possible manager and employee value intersections, and the geometry of the alignment vector designates optimal alignment between employee and manager for each stage of job performance from entry to advancement. The plotted position of an employee on the array in relation to its location and distance from the alignment vector measures employee performance, potential, and risk, and indicates the direction and extent of adjustment needed by either employee or manager to achieve and maintain alignment.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 8, 2020
    Assignee: EffectiveTalent Office LLC
    Inventor: Craig M. Watson
  • Patent number: 10733353
    Abstract: A method for forming an integrated device includes the following operations. A first circuit layout is provided. The first circuit layout includes a first device and a connecting portion. A first voltage level is applied to the first circuit layout. The first circuit layout is analyzed according to the first voltage level to determine if a failing signal occurs in the first circuit layout. The first device is analyzed when the failing signal occurs. It is determined, according to a second voltage level, whether a violation occurs in the first device. The first circuit layout is modified when a violation occurs.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Tao Yang, Yung-Chow Peng
  • Patent number: 10719656
    Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexey Y. Lvov, Gi-Joon Nam, Gustavo Enrique Tellez
  • Patent number: 10706201
    Abstract: Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yi-Xiao Ding, Mehmet Can Yildiz
  • Patent number: 10691859
    Abstract: A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Woo Seo, Ha-Young Kim, Hyun-Jeong Roh
  • Patent number: 10684862
    Abstract: A processor synthesis device inserts a stop circuit into a circuit configuration, which is defined by processor model information and includes a plurality of operators, based on instruction set information that defines an instruction set including a plurality of instructions, the stop circuit stopping an operator not used in an instruction to be executed among the plurality of operators when each of the plurality of instructions is executed. The processor synthesis device generates processor synthesis information which is an RTL description defining a circuit configuration into which the stop circuit is inserted.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 16, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takumi Hoshi, Tetsuo Yano, Hiroyuki Yamamoto, Seidai Takeda
  • Patent number: 10565348
    Abstract: A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10468426
    Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 5, 2019
    Assignee: Synopsys, Inc.
    Inventor: Andrew E. Horch
  • Patent number: 10366200
    Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10346579
    Abstract: Embodiments relate to an interactive routing of connections in a circuit where connections associated with an initial pin of a circuit element (e.g., a row of FinFETs) are replicated in association with at least one other pin of the circuit element or a different circuit element in the circuit. The replication of connections can be performed intelligently by taking into account mapping of pins as well as design rules or other restrictions imposed on the circuit. The connections can be in form of trunks and branches, and are displayed as user inputs are received. A digital representation of the circuit with the connections as displayed is also generated. At least some of the connections in the circuit are replicated without individual user inputs based on user inputs associated with a connection to the initial pin.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 9, 2019
    Assignee: Synopsys, Inc.
    Inventors: Philippe Aubert McComber, Hsiang-Wen Jimmy Lin
  • Patent number: 10340180
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Martin J. O'Toole, Terry A. Spooner, Jason E. Stephens
  • Patent number: 10325052
    Abstract: The present embodiments relate generally to techniques for creating and/or modifying multi-layer buses in an IC design. According to some more particular aspects, embodiments relate to techniques for allowing an IC designer to efficiently transition a multi-layer bus section made of N wires and M layers to another multi-layer bus section made of N wires and any other M? layers. In some embodiments, the user describes, programmatically, one or several custom transitions called a custom transition procedure and saved in a human-readable text file that can also be read by a layout editor tool. By a command associated with the custom transition procedure that is exposed to the user in the layout editor tool, a multi-layer bus is automatically transitioned from a set of layers to another.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: June 18, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Christophe Fouassier
  • Patent number: 10312441
    Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jean Fompeyrine, Stefan Abel, Veeresh Vidyadhar Deshpande
  • Patent number: 10248749
    Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
  • Patent number: 10229239
    Abstract: A global router determines edge capacity of global tiles for a first integrated circuit. The global router determines a respective edge capacity of minimum width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit. Next, the global router determines a respective edge capacity of non-minimum width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit. The edge capacities for minimum width and non-minimum width wire tracks are determined in separate operations.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Diwesh Pandey, Christian Schulte, Gustavo E Tellez
  • Patent number: 10176288
    Abstract: The present disclosure relates to a system and method for modeling the placement of components in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design at a graphical user interface (GUI) and a selection for a component to be placed within the electronic circuit design. Embodiments may also include detecting a change in the position of the selected component to determine when the selected component is moved into a zone of the electronic circuit design. Embodiments may further include determining a component footprint and one or more padstacks associated with the component footprint for the selected component based upon the position of the selected component within the zone of the electronic circuit design. Embodiments may also include rendering the component footprint and the padstacks on the selected component based upon, at least in part, the position of the selected component.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 8, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Brian James Carlson, Frank X Farmar, Robert Paul White, Amey Vilas Joshi, Edmund J. Hickey
  • Patent number: 10169519
    Abstract: Respective large block synthesis (LBS) blocks of an integrated circuit (IC) are overlapped along a corner of each respective LBS block to form an overlap area having an area less than respective areas of respective LBS blocks that are overlapped. A first portion of the overlap area is allocated to a first LBS block and configured to be used by the first LBS block, and a second portion of the overlap area is allocated to a second LBS block and configured to be used by the second LBS block.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Harry Barowski, Harald D. Folberth, Joachim Keinert, Sourav Saha
  • Patent number: 10102328
    Abstract: The present disclosure relates to a system and method for constructing spanning trees. Embodiments may include receiving, using at least one processor, a plurality of nodes associated with the integrated circuit design. In some embodiments, the plurality of node may be configured to be intercoupled by one or more combinations of edges. Embodiments may further include receiving a user-defined value at a graphical user interface. Embodiments may also include generating a routing graph with a subset of the one or more combinations of edges based upon, at least in part, the user-defined value and the position of each of the plurality of nodes. Embodiments may further include generating a spanning tree based upon, at least in part, at least one of: one or more wirelengths of the routing graph and one or more source-sink detour costs associated with the routing graph.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 16, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wen-Hao Liu, Zhuo Li, Charles Jay Alpert, Mehmet Can Yildiz
  • Patent number: 10099429
    Abstract: Systems, media, and methods for modeling electronic products for 3D printing including providing a library of modules and module interfaces; receiving at least one ruleset; receiving preliminary substrate structure data, the preliminary substrate structure data comprising shape and volume data defining a substrate; providing an interface allowing the user to place one or more modules on the substrate; providing an interface allowing the user to place one or more module interfaces, the module interfaces coupling one or more modules together through the substrate; warning the user where placement of a module or module interface violates the at least one ruleset; generating routing of electrically conductive interconnects between placed module interfaces; and generating a finalized substrate structure model by combining the preliminary substrate structure data with module placement data and interconnect routing data.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: October 16, 2018
    Assignee: Facebook, Inc.
    Inventors: Baback Elmieh, Saurabh Palan, Andrew Alexander Robberts, Alexandre Jais
  • Patent number: 9984482
    Abstract: In a general aspect, a method includes displaying a first component of a graph on a user interface, including displaying at least one port of the first component; responsive to a user interaction with the displayed first component, displaying a representation of one or more ports of the first component that is distinct from the display of the first component; and enabling the user to generate a connection between the representation of a particular one of the ports of the first component and a port of a second component of the graph.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: May 29, 2018
    Assignee: Ab Initio Technology LLC
    Inventors: Erik Bator, Ilya Rozenberg, Daniell Stevens, Dan Teven, Fredric M. White
  • Patent number: 9977851
    Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
  • Patent number: 9972566
    Abstract: An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar, Tingdong Zhou
  • Patent number: 9922158
    Abstract: According to an aspect, a plurality of nets are grouped into a plurality of buckets based on timing criticalities associated with the nets, and different TCRs are assigned to each of the buckets. For each of the nets, a TCR for the net is determined based on the TCR assigned to the bucket containing the net. Global routing of the net is performed according to the TCR and to one or more constraints associated with the net. The TCR for the net is incremented by a specified amount in response to the global routing of the net resulting in violating at least one of the one or more constraints associated with the net and to a stopping criteria not being met. The performing global routing and incrementing the TCR for the net is repeated.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diwesh Pandey, Sven Peyer, Yaoguang Wei
  • Patent number: 9922002
    Abstract: One embodiment of the present invention provides a computing system. The computing system includes a processor and a computer-readable storage medium. The computer-readable storage medium stores instructions which when executed by the processor cause the processor to perform a method. The method comprises obtaining from a first data structure one or more pointers to corresponding elements in a second data structure. A respective vertex of a graph corresponds to an element in the first data structure and the graph supports multiple edge types between respective vertex pairs. The method further comprises obtaining from the second data structure a respective edge type associated with a respective vertex and a respective successor vertex of the edge type and enumerating a respective successor vertex of an edge type of a vertex from the second data structure based on a pointer in an element in the first data structure associated with the vertex.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 20, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Rong Zhou, Daniel Davies
  • Patent number: 9892224
    Abstract: A method of forming a set of masks for manufacturing an integrated circuit includes determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design. The first via layout pattern and the power rail layout pattern overlap each other. The first via layout pattern is part of a first cell layout of the original layout design. The power rail layout pattern is shared by the first cell layout and a second cell layout of the original layout design. The method further includes modifying the original layout design to become a modified layout design and forming the set of masks based on the modified layout design. The modifying the original layout design includes, if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiung Lin, Ta-Pen Guo, Yi-Hsun Chiu
  • Patent number: 9865355
    Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yafeng Zhang, Liang Qiao, Chunyuan Hou, Jun Xu
  • Patent number: 9843332
    Abstract: Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: December 12, 2017
    Assignee: Altera Corporation
    Inventors: Ramanand Venkata, Dana How, Christopher Lane
  • Patent number: 9817941
    Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 14, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Mark Edward Rossman
  • Patent number: 9747397
    Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: August 29, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Sivaprakasam Sunder, Kirk Schlotman