Abstract: A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

Abstract: A computer-implemented method, a machine learning system, and non-transitory computer-readable storage medium for designing electrical circuits are provided. In the computer-implemented method input data is received and processed to generate a representation of the electrical circuit. A plurality of candidate routes for connecting a first and second circuit element of the electrical circuit are identified. A candidate route is then selected by iteratively selecting candidate sub-routes. Selecting candidate sub-routes is performed by using a Sequential Monte Carlo process to perform a look ahead search of a subset of the plurality of candidate routes, the Sequential Monte Carlo process being guided by a neural network. The representation of the electrical circuit is then updated with an action selection signal representing a selection of a candidate sub-route.

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

Abstract: Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

Abstract: Various embodiments of a method and apparatus for estimating the effective resistance for the design of on-chip power nets are disclosed. Through sampled node resistance, performance of a power net can be determined on an entire chip. Effective resistance predictions can be made for all nodes. Through the resistance predictions, a designer can analyze the which areas would benefit from power and ground augmentation.

Abstract: A computer-implemented method, a system, and non-transitory computer-readable storage medium for designing electrical circuits are provided. In the method input data is received and processed to generate a representation of the electrical circuit. A first process is repeatedly performed to identify a plurality of candidate routes for connecting a first and second circuit element based on the representation. A candidate route is selected from the plurality of candidate routes based on a look ahead search. The first process includes selecting a first point in the representation, executing a second process to identify a set of candidate points, and selecting a second point from the set of candidate points. The second process comprises evaluating at least one candidate path extending in a linear direction from the first point to identify the set of candidate points based on at least a constraint and a topology of the electrical circuit.

Abstract: Geometric extraction is performed on an unstructured document by recognizing textual blocks on at least a portion of a page of the unstructured document, generating bounding boxes that surround and correspond to the textual blocks, determining search paths having coordinates of two endpoints and connecting at least two bounding boxes, and generating a graph representation of the at least a portion of the page, the graph representation including the plurality of textual blocks, the coordinates of the vertices of each bounding box and the coordinates of the two endpoints of each search path.

Abstract: Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed on one or more processors, cause the one or more processors to perform operations. The operations include generating a plurality of child processes according to a number of a plurality of partitions in an integrated circuit (IC) design for an IC die, each of the plurality of child processes corresponding to and assigned to a respective one of the plurality of partitions. The operations include transmitting each of the plurality of partitions to a respective one of the plurality of child processes for routing, each of the plurality of partitions comprising a placement of components for the IC design. The operations include receiving a plurality of routings from the plurality of child processes. The operations include merging the plurality of routings into a global routing for the IC design by assembling together to form a global routing.

Abstract: Technologies are described for determining possible routes using pre-processing operations. The pre-processing operations determine possible routes from an origin location to a destination location by dynamically generating representations of the transportation networks at runtime. For example, the pre-processing operations can dynamically determine a geographic area, and/or multiple sub-areas, that covers the origin location and the destination location. Possible routes from the origin location to the destination location can then be determined using only those locations within the geographic area and/or sub-areas. The locations that make up the possible routes can be provided for route optimization that utilizes transportation schedules and/or additional transportation requirements.

Abstract: To determine a three-dimensional layout of electrical connections of an electric component, a processor executes a path optimization routine to determine three-dimensional routes for a plurality of electrical connections of the electric component. A conflict management is performed to generate conflict-free three-dimensional routes for the plurality of electrical connections.

Abstract: A method for generating an executable program to run on a system of one or more processor chips each comprising a plurality of tiles. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and directional edges, wherein the graph is received in a first graph format that does not specify which data nodes and vertices are allocated to which of the tiles; and generating an application programming interface, API, for converting the graph, to determine a tile-mapping allocating the data nodes and vertices amongst the tiles. The generating of the API comprises searching the graph to identify compute vertices which match any of a predetermined set of one or more compute vertex types. The API is then called to convert the graph to a second graph format that includes the tile-mapping, including the allocation by the assigned memory allocation functions.

Abstract: A method for generating an executable program to run on a system of one or more processor chips each comprising a plurality of tiles. The method comprises: receiving a graph comprising a plurality of data nodes, compute vertices and directional edges, wherein the graph is received in a first graph format that does not specify which data nodes and vertices are allocated to which of the tiles; and generating an application programming interface, API, for converting the graph, to determine a tile-mapping allocating the data nodes and vertices amongst the tiles. The generating of the API comprises searching the graph to identify compute vertices which match any of a predetermined set of one or more compute vertex types. The API is then called to convert the graph to a second graph format that includes the tile-mapping, including the allocation by the assigned memory allocation functions.

Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein a bin size of a higher larger of the metal layers has a greater bin size than that of a lower layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.

Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

Abstract: A layout method of a semiconductor device is disposed. The layout method includes: disposing a first metal strip directed to a first clock signal and disposing a first block strip parallel with the first metal strip, wherein the first block strip is indicative of a first blockage which prevents a routing tool from placing another metal strip on the location of the first block strip.

Abstract: A method of modifying a cell includes determining a number of pins in a maximum overlapped pin group region. The method further includes determining a number of routing tracks within a span region of the maximum overlapped pin group region. The method further includes comparing the number of pins and the number of routing tracks within the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.

Abstract: Techniques for grouping and labeling Internet of Things (IoT) devices are disclosed. In accordance with an aspect of the invention, there is provided a computer program product configured to be operable to perform the techniques described in this paper to enable grouping and labeling of IoT devices. As devices are grouped and labeled, and behavior is matched to or deviates from known or expected behavior, the network can be more readily understood and alerts can be more timely and appropriate.

Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design using track patterns while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. According to some aspects, the present embodiments provide “Dynamic Width Space Patterns (DWSP)” which are WSPs that are modified dynamically in consideration of neighboring geometries such that shapes created or edited using WSPs are design rule compliant. Embodiments can include providing visual indicators in a display of a portion of a design that is being created or edited, as well as possibly other alerts, so as assist a designer in creating a design rule compliant integrated circuit design that is also subject to WSPs.

Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance. Metal line material is deposited into a set of openings in a dielectric layer of the integrated circuit, the set of openings corresponding to the second arrangement of metal lines.

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

Abstract: A computer implemented method for routing a multitude of conductors through a first routing area on a planar surface is presented. The method includes receiving data representing the first routing area bounded by two opposite longitudinal sides each having a different number of a multitude of first vertices. The first routing area includes one or more blockages. The method further includes determining one or more locations on at least one of the two opposite longitudinal sides for adding one or more second vertices, and decomposing the first routing area into a multitude of second routing areas each not including any of the one or more blockages. The method further includes performing a gateway model routing (GMR) of the multitude of conductors in each of the multitude of second routing areas using the multitude of first vertices and the added one or more second vertices.

Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein the bin sizes are progressively larger from a bottom layer to a top layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

Abstract: A system and method for rip-up and re-routing a global routing solution includes determining, via processing circuitry, one or more rip-up and re-route (R&R) strategies for a net; decomposing, via the processing circuitry, multiple pins of the net into a plurality of subnets; decomposing a spanning tree of the net into paths for the plurality of subnets; determining, via the processing circuitry, a probability of success of each of the R&R strategies for one of minimizing a total overflow of a global routing solution or minimizing a wire length of the global routing solution; and applying one of the R&R strategies to the net based on the determined probability of success of said each of the R&R strategies towards improving the global routing solution, wherein the global routing solution includes a plurality of spanning trees for a respective plurality of nets of a global routing system.

Abstract: A system and method for rip-up and re-routing a global routing solution includes determining, via processing circuitry, one or more rip-up and re-route (R&R) strategies for a net; decomposing, via the processing circuitry, multiple pins of the net into a plurality of subnets; decomposing a spanning tree of the net into paths for the plurality of subnets; determining, via the processing circuitry, a probability of success of each of the R&R strategies for one of minimizing a total overflow of a global routing solution or minimizing a wire length of the global routing solution; and applying one of the R&R strategies to the net based on the determined probability of success of said each of the R&R strategies towards improving the global routing solution, wherein the global routing solution includes a plurality of spanning trees for a respective plurality of nets of a global routing system.

Abstract: A workflow engine processes a work problem to generate solutions for the work problem comprising a plurality of related optimization problems. The work problem may comprise a second optimization problem that is dependent on a first optimization problem, such that at least one solution for the first optimization problem is to be utilized as an initial solution for the second optimization problem. The workflow engine generates and stores a branch object for each optimization problem, each branch object specifying a solver engine assigned for processing the optimization problem and dependency information indicating a dependency relationship between the optimization problem and another optimization problem. The workflow engine processes the work problem based on the branch objects by initiating each solver engine to perform optimization operations on the assigned optimization problem based on the corresponding branch object to generate one or more solutions for the assigned optimization problem.

Abstract: Systems and methods for using logic design processing to create an integrated circuit (IC).

Abstract: Techniques and systems for determining a route from a start point to a target point in an integrated circuit (IC) design using topology-driven line probing are described. Some embodiments can create a data structure to store a set of nodes, wherein each node is located on a horizontal probe or a vertical probe, and wherein each node has a cost. The embodiments can then perform a set of operations in an iterative loop, the set of operations comprising: selecting a lowest cost node from the set of nodes; terminating the iterative loop if the lowest cost node is located at the target point; extending a probe from the lowest cost node if the lowest cost node is not located at the target point; creating at least one new node on the probe or on an ancestor of the probe; and adding the new node to the set of nodes.

Abstract: Systems and methods for real-time mapping using geohashing are described. In an example implementation, a method includes receiving current location data from a first computing device in real-time, mapping the current location data in a map that includes collected location data from a second computing device, generating a heat map based on the current location data and the collected location data, determining a line using the generated heat map, and providing a route suggestion based on the determined line to the first computing device.

Abstract: A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.

Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.

Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

Abstract: A method includes accessing a design data of an integrated circuit (IC), the design data including a plurality of layers. For each of the layers, the method performs: assigning a bin size of the respective layer based on a layout property of the respective layer; and performing a bin-based feature allocation according to the assigned bin size. The method also includes updating the design data according to the bin-based feature allocation. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.

Abstract: A photonic circuit design system includes a photonic circuit design tool to facilitate user inputs to generate a photonic circuit netlist comprising a photonic design component of a photonic circuit design. The system includes a memory system to store the photonic circuit netlist and a component library comprising a plurality of predetermined photonic design components from which the photonic design component is selected. The component library further includes physical data associated with physical characteristics of the plurality of predetermined photonic design components.

Abstract: A router is used to produce a first integrated circuit structure according to an engineering change order. An initial detail routing topology is imported for the first integrated circuit structure. An engineering change order is received instructing the router to change a portion of the initial detail routing topology for the first integrated circuit structure. A global routing operation is performed which routes global wires for the portion of the initial detail routing topology for the first integrated circuit structure. For each global wire which is routed, a specific global wiring track is selected for the global wire within each edge of a set of global tiles in a routing topology for the first integrated circuit.

Abstract: A method of modifying a cell includes identifying a maximum overlapped pin group. The method further includes determining a number of pins in the maximum overlapped pin group. The method further includes determining a span region of the maximum overlapped pin group. The method further includes comparing the number of pins and the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold. The method further includes fabricating a mask based on the increased length of the at least one pin.

Abstract: A method of selecting routing resources in a multi-chip integrated circuit device is described. The method comprises placing a design on the multi-chip integrated circuit device; estimating a number of vias required to enable connections between chips of the multi-chip integrated circuit device that is placed with a portion of the design; identifying an area of a chip having a number of vias that is greater than a maximum number of vias for the area of the chip; selecting a partition window defining resources in the chip that is placed with the portion of the design, where in the partition window is selected to allow the number of vias to meet a maximum requirement of vias for the partition window; and re-placing the portion of the design within the partition window so that the number of vias in the area of the chip is within the maximum number of vias for the area.

Abstract: Aspects of the present disclosure address improved systems and methods for routing topology generation. More specifically, the present disclosure addresses systems and methods for generating a routing topology using a spine-like tree structure. Consistent with some embodiments, given a Steiner-tree based routing topology as input, the system performs an iterative refinement process on the tree topology where at least a portion of subtrees are converted to spine subtrees as the system traverses the nodes of the tree in a particular traversal order. This process continues until all tree nodes have been processed. The result is a refined routing topology that has a spine-like structure.

Abstract: Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.

Abstract: A computer-implemented technique for orthogonal edge routing of directed layered graphs with edge crossings reduction is presented. The pre-arranged nodes are positioned on a rectangular grid consisting of layers across the flow direction and lanes along the flow direction. The layers are separated by rectangular regions defined as layer pipes, and the lanes are separated by rectangular regions defined as lane pipes. Each pipe contains one or more ordered segment tracks. The edges are routed along the shortest paths as orthogonal polylines composed of chained line segments. Each segment is assigned to a pipe. The segments within a pipe are positioned on segment tracks. The edge crossings reduction phase contains iterative procedures to resolve intersections between segments. To resolve the crossings between edges the pairs of conflicting segments are swapped or segments are repositioned on adjacent segment tracks, effectively rubber banding the segments while considering the shortest paths of edges.

Abstract: A system and method for rip-up and re-routing a global routing solution includes determining, via processing circuitry, one or more rip-up and re-route (R&R) strategies for a net; decomposing, via the processing circuitry, multiple pins of the net into a plurality of subnets; decomposing a spanning tree of the net into paths for the plurality of subnets; determining, via the processing circuitry, a probability of success of each of the R&R strategies for one of minimizing a total overflow of a global routing solution or minimizing a wire length of the global routing solution; and applying one of the R&R strategies to the net based on the determined probability of success of said each of the R&R strategies towards improving the global routing solution, wherein the global routing solution includes a plurality of spanning trees for a respective plurality of nets of a global routing system.

Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.

Abstract: A high-speed shape-based router is applicable to standard-cell digital designs, chip-level-block assembly designs, and other styles of design. In a flow of the invention, the technique establishes an initial structure for each net to be routed. Nets or parts of them are ordered. Each part of the net may be routed using a spine routing search, depth first search, or a space flood search, or any combination of these. Where sections fail or an error occurs, conflicts are identified, and the technique tries routing again.

Abstract: Various embodiments provide for clustering pins of a circuit design for connection to a power-ground network (PG) of the circuit design using a nearest neighbor graph. Pin clustering, according to some embodiments, can minimize wirelength, minimize a number of vias, satisfy constraints relating to a pin count (e.g., maximum number of pins per power-ground access point), and satisfy constraints relating to a bounding box size.

Abstract: A flexible tile-based place-and-route methodology utilizes pre-generated physical layer (PHY) tiles to greatly simplify the task of automatically generating routing solutions between associated PHYs disposed on a memory device and a corresponding processor for any selected floorplan positioning of the memory device relative to the corresponding processor. The PHY tiles are pre-generated software-based layout descriptions that model the densely-packed 2D contact PHY pad arrays, and also comprise partial layout features including signal line segments that escape routing pins from the 2D contact pads to an orthogonal (straight-line) edge of the PHY tile and disposed in design-rule-compliant spaced-apart arrangements. Optional 45-degree jog line segments are utilized to efficiently correct for alignment offsets between the memory PHY and processor PHY.

Abstract: Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.