System-on-chip Design Patents (Class 716/138)
  • Patent number: 10262163
    Abstract: A cryptographic ASIC and method for autonomously storing a unique internal identifier into a one-time programmable memory in isolation by a foundry. The identifier may be determined by calculating a transformed hash of a predetermined input, and may serve as a cryptographically defined and verifiable CpuID for a particular ASIC instance. The CpuID may be derived from an input based on a manufacture date, a wafer lot number, a wafer number, row and column coordinates for a die on a wafer, or other foundry-defined data. The CpuID enables a given ASIC instance to be securely and remotely identified across an untrusted network, and to serve as a specified processor that originates an information stream or a message. The ASIC need not always perform high-speed calculations and so may be relatively simple and inexpensive, and in one embodiment serves as a secure data administrator that manages subscriptions and software updates.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 16, 2019
    Assignee: Blockchain ASICs LLC
    Inventor: Edward L. Rodriguez De Castro
  • Patent number: 10218359
    Abstract: Devices and methods for reconfiguring a programmable fabric include identifying resources in a programmable fabric of the programmable device as belonging to a partition. Reconfiguring the programmable fabric also includes creating a mask for the partition that indicates that the identified resources belong to the partition. Reconfiguring the partition also includes reconfiguring resources, via a configuration controller, in programmable fabric associated with the partition using the mask without changing resources associated with other partitions in the programmable fabric.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Andrew Draper
  • Patent number: 10210116
    Abstract: In certain aspects of the disclosure, an apparatus includes first and second semaphore registers disposed in a first power domain. A common address bus is coupled to the first and second semaphore registers, and a semaphore lock is disposed in the first power domain and coupled to the first and second semaphore registers. The semaphore lock is controlled by the first and second semaphore registers, and controls whether a signal from a second power domain is permitted to propagate to the first power domain. The first and second semaphore registers may be associated with first and second register addresses, respectively, which are selected to provide a substantially maximized Hamming distance between them. The first and second semaphore registers may have a write order expectation enforced between them.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Michael Kevin Batenburg, Vincent Pierre Le Roy, Praveen Kumar Origanti
  • Patent number: 10205440
    Abstract: Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Basannagouda Somanath Reddy, Deepak D. Sherlekar, Princy K. Varghese
  • Patent number: 10102326
    Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 16, 2018
    Assignee: Altera Corporation
    Inventors: Mark Stephen Wheeler, Gordon Raymond Chiu
  • Patent number: 9697312
    Abstract: A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further includes a design module to generate a design for the designed circuit based on the specification data, and an output module to set parameters of at least one of the analog elements based on the design. Other embodiments are also provided.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: July 4, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: David A LeHoty, Antonio Visconti
  • Patent number: 9690733
    Abstract: An information processing apparatus includes a control unit configured to activate the information processing apparatus in a first activation mode or a second activation mode, a receiving unit configured to receive an operation for activating the information processing apparatus in the first activation mode from a user, a notification unit configured to notify the control unit of information corresponding to the operation of the user received by the receiving unit, and a connection unit configured to connect the control unit and the receiving unit without connecting the notification unit and to notify the control unit that a user has operated on the receiving unit, wherein the control unit activates, in the case where it is not notified via the connection unit that a user has operated on the receiving unit, the information processing apparatus in the second activation mode without waiting for activation of the notification unit.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 27, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Xiaoli Wang
  • Patent number: 9652424
    Abstract: An information processing apparatus includes a control unit configured to activate the information processing apparatus in a first activation mode or a second activation mode, a receiving unit configured to receive an operation for activating the information processing apparatus in the first activation mode from a user, a notification unit configured to notify the control unit of information corresponding to the operation of the user received by the receiving unit, and a connection unit configured to connect the control unit and the receiving unit without connecting the notification unit and to notify the control unit that a user has operated on the receiving unit, wherein the control unit activates, in the case where it is not notified via the connection unit that a user has operated on the receiving unit, the information processing apparatus in the second activation mode without waiting for activation of the notification unit.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 16, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Xiaoli Wang
  • Patent number: 9183331
    Abstract: A system and method that tests an IP component of a hardware design generates an abstract model of the IP component based on knowledge of the design and one or more protocols implemented with the IP component. A generic driver and associated interfaces are additionally generated or selected to test the IP component within the hardware design.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 10, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Guoqing Zhang, Erik S. Panu, Levent Caglar
  • Patent number: 9015647
    Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Gerald Suiter, Henry Potts
  • Patent number: 9009648
    Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: April 14, 2015
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Mahmud Hassan, Sundari Mitra, Joseph Rowlands
  • Patent number: 8943457
    Abstract: An aspect of the present invention replaces memory elements in a scan chain with corresponding new (memory) elements, with each new element having two paths to provide the corresponding data output. One of the two paths is operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path is operable to connect the data value to the next element in the chain during a shift phase of said test mode. As a result, unneeded transitions/evaluations in the combinational logic are avoided during shift time, thereby reducing the resource requirements in the corresponding duration. However, the further processes (including various design phases and fabrication) are continued based on the original data (i.e., without the new elements) such that unneeded delays are avoided during the eventual operation in functional mode of the various fabricated IC units.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: January 27, 2015
    Assignee: NVIDIA Corporation
    Inventors: Amit Dinesh Sanghani, Punit Kishore
  • Patent number: 8904333
    Abstract: A system for prototyping an integrated circuit (IC) that has a mixed signal intellectual property (IP) core includes implementing the IP core using discrete programmable digital ICs and discrete analog ICs by partitioning the IP core into a digital IP portion and an analog IP portion.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Haifeng Bai, Yin Guo, Xuewen He, Kun Wu, Lei Zhang, Shayan Zhang
  • Patent number: 8898613
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 8875079
    Abstract: A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 28, 2014
    Assignee: LSI Corporation
    Inventor: Douglas J. Saxon
  • Patent number: 8875083
    Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Synopsys, Inc.
    Inventors: Chen-Feng Chang, Chin-Fang Shen, Hsien-Shih Chiu, I-Jye Lin, Tien-Chang Hsu, Yao-Wen Chang, Chun-Wei Lin, Po-Wei Lee
  • Patent number: 8869086
    Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 21, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: Gene D. Tener, Mark A. Goodnough, Jennifer K. Park, Walter David Borowski
  • Patent number: 8867086
    Abstract: There is provided a mechanism of preferentially using a memory layer which suffers a small influence of heat of an SOC die, based on the positional relationship between the SOC die and the memory layer, and decreasing the refresh frequency of the DRAM and a leakage current. To accomplish this, an information processing apparatus allocates, in order to execute an accepted job, a memory area for executing the job preferentially from a memory physically farthest from the SOC die among a plurality of memories, and then executes the job.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 21, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tsuyoshi Mima
  • Patent number: 8863072
    Abstract: Various embodiments of the present disclosure provide techniques for producing configuration images of a system on a chip (SOC) design, including a programmable logic device (PLD) and operating system (OS) packages, responsive to a user selection of one or more modules of the PLD and a user selection of at least one OS package. A processor configured to run a design tool, builds the configuration image of the SOC. The design tool compiles a PLD configuration image corresponding to the first selection, selects one or more PLD module drivers corresponding to the first selection, compiles a bootloader and OS kernel design corresponding to the selected one or more module drivers and the PLD image; and builds the configuration image of the SOC corresponding to the bootloader and OS kernel design and the second selection.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: October 14, 2014
    Assignee: Altera Corporation
    Inventor: Steve Jahnke
  • Patent number: 8863060
    Abstract: An Infrastructure Description Language (IDL) includes Service Level Hints (SLHs) and Service Level Requirements (SLRs). The SLHs and SLRs are used to configure at least one hardware resource in a computing system having an intelligent configurator to broker a hardware configuration based on the SLHs and SLRs.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Arun S. Jagatheesan, Zheng Li
  • Patent number: 8856714
    Abstract: A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Sun Hwang, Sung-Hee Yun, Jae-Hoon Jeong, Won-Cheol Lee, Tae-Heon Lee, Young-Hoe Cheon
  • Patent number: 8850381
    Abstract: The present patent document relates to a method and apparatus for an automatic clock to enable conversion for FPGA-based prototyping systems. A library or netlist is provided having a plurality of state elements of a chip design to be prototyped by a user. The chip design can have dozens of different user clocks and clock islands using these different user clocks. The state elements of an element library or netlist are converted to a circuit having one or more state elements and other logic that receive both a user clock as well as a fast global clock. With the disclosed transformations, the functionality of the original state element is maintained, and a single or low number of global clocks can be distributed in an FPGA of the prototype with user clocks generated locally on the FPGA.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Subramanian Ganesan, Philip Henry Nils Anthony De Buren, Jinny Singh, David Abada
  • Patent number: 8826221
    Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 2, 2014
    Assignee: DECA Technologies Inc.
    Inventors: Christopher M. Scanlan, Timothy L. Olson
  • Patent number: 8826203
    Abstract: A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: John Darringer, Jeonghee Shin
  • Patent number: 8826199
    Abstract: Methods, systems, and computer readable medium for developing a system architecture that involves defining resource constraints for kinds of resources and constraint values for optimization parameters, and defining a design space as variants, where each variant is a vector. Satisfying sets of variants are determined for optimization parameters by assigning membership values to each variant of a universe of discourse set and performing a fuzzy search of a universe of discourse set using the corresponding membership values. A set of variants is determined based on an intersection of the satisfying sets of variants. An ordered list of variants is generated by sorting the set of variants and a variant is selected based on a position of the variant in the ordered list for use in developing the system architecture.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 2, 2014
    Assignee: Ryerson University
    Inventors: Reza Sedaghat, Anirban Sengupta
  • Patent number: 8819616
    Abstract: Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 26, 2014
    Assignee: NetSpeed Systems
    Inventors: Joji Philip, Sailesh Kumar, Eric Norige, Mahmud Hassan, Sundari Mitra
  • Patent number: 8813014
    Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang
  • Patent number: 8781783
    Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: July 15, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Hsien-Chuan Liang, Shen-Chun Li, Chun-Jen Chen, Shou-Kuo Hsu, Yung-Chieh Chen, Wen-Laing Tseng
  • Patent number: 8782593
    Abstract: A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information. A thermal resistance-network (R-network) is generated from the decrypted first component information. A temperature map of the package is generated using the thermal R-network and a second component information of an unsecured portion of the package, wherein the secured portion and the unsecured portion are bonded to each other.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Meng-Fu You, Po-Hsiang Huang, Cheng-Chieh Hsieh
  • Patent number: 8769477
    Abstract: A user interface for a computer-aided design tool includes a display. The display includes a visualization of a processor system of a system-on-a-chip (SOC). The visualization includes a plurality of blocks and each block represents a component of the processor system. Each block visually indicates a configuration status of the component represented by the block.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Yogesh Gathoo, Siddharth Rele, Gregory A. Brown, Avdhesh Palliwal, Gangadhar Budde, Sumit Nagpal
  • Patent number: 8769448
    Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Nabeel Shirazi, Sean P. Caffee
  • Patent number: 8762927
    Abstract: Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed at the same time by transmitting and receiving the circuit design information relating to the printed boards and the layout design information relating to the printed boards between the circuits and layouts relating to the printed boards.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: June 24, 2014
    Assignee: Zuken Inc.
    Inventor: Satoshi Nakamura
  • Patent number: 8751992
    Abstract: According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuaki Utsumi, Naoyuki Kawabe, Keiji Omotani
  • Publication number: 20140157223
    Abstract: In various embodiments, an integrated circuit layout is disclosed. In one embodiments, the integrated circuit layout comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area comprises a non-zero, non-opposing effect with respect to the first contact area. The first contact area and the second contact area comprise a first distance. When the first distance is below a predetermined threshold the first logic cell and the second logic cell are placed along a first R-line of the circuit and a third contact area comprising an opposing effect with respect to the first contact area and the second contact area is placed between the first contact area and second contact area.
    Type: Application
    Filed: October 22, 2013
    Publication date: June 5, 2014
    Inventor: Klas Olof Lilja
  • Patent number: 8745557
    Abstract: A system and method optimizes hardware description code generated from a graphical program or model automatically. The system may include a streaming optimizer, and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The streaming optimizer may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: June 3, 2014
    Assignee: The MathWorks, Inc.
    Inventors: Girish Venkataramani, Kiran Kintali, Pieter J. Mosterman
  • Patent number: 8745570
    Abstract: A present ASIC may include functionality exceeding that which will be operative at one given time (e.g., when the chip is packaged and inserted into a broader circuit). The excess ASIC functionality may be chosen in anticipation of changing market environments, and/or differing product requirements in various market spaces (e.g., in different countries where different interoperability standards are chosen). In such cases, an appropriate subset of the excessive ASIC functionality may be programmably activated for each market space after manufacture.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: June 3, 2014
    Assignee: Sheyu Group, LLC
    Inventor: James T. Koo
  • Patent number: 8713504
    Abstract: A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This substitution may occur permanently or temporarily. When an ASIC block is temporarily substituted, faulty outputs of the ASIC block are disabled just at the time they would otherwise propagate an error. The operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed programmable logic. Thus, a fault-infected ASIC block that operates improperly 1% of the time can continue to be gainfully used for the 99% of the time when its operations are fault free. This substitution can be activated in various stages of the ASIC block's life including after: initial design; pilot production; and mass production. This provides for cost saving and faster time-to-market, repair, and maintenance even years after installation and use.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: April 29, 2014
    Assignee: Sheyu Group, LLC
    Inventor: James T. Koo
  • Patent number: 8689160
    Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 1, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chang Tzu Lin, Ding Ming Kwai
  • Patent number: 8683412
    Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Miles P. McGowan
  • Patent number: 8677298
    Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify critical and near-critical cyclic logic paths within the user logic design, applying timing optimizations to the critical and near-critical cyclic logic paths, and retiming logic paths other than the critical and near-critical cyclic logic paths.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: March 18, 2014
    Assignee: Altera Corporation
    Inventors: Valavan Manohararajah, David Lewis, David Galloway, Ryan Fung
  • Patent number: 8664974
    Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Tabula, Inc.
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
  • Patent number: 8667446
    Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: March 4, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
  • Patent number: 8661400
    Abstract: A graphical user interface for tuning a programmable device comprises a first on-screen window comprising a representation of a target apparatus, wherein the target apparatus comprises the programmable device, and a second on-screen window configured to appear in response to a selection of a graphical element associated with the representation of the target apparatus, wherein the second on-screen window comprises graphical user interface (GUI) display elements representing a plurality of parameter values presently controlling operation of a device corresponding to the selected graphical element. The second on-screen window is further configured to accept a modification of at least one of the plurality of parameter values via the GUI display elements, initiate communication of the modification to the programmable device, and in response to implementing the modification in the programmable device, display operational results of the device as modified by the modification.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: February 25, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenneth Y. Ogami, Marat Zhaksilikov, Andrew Best
  • Patent number: 8661402
    Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: February 25, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
  • Patent number: 8661399
    Abstract: Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague
  • Patent number: 8656325
    Abstract: Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: John E. Barwin, Amol A. Joshi, Baozhen Li, Michael R. Ouellette
  • Patent number: 8650528
    Abstract: It is possible to improve workability of a design work by handling electric information between one object and other objects associated with the object. A plurality of objects are inputted and electric information is inputted to the objects. Among the objects, mutually connected objects are virtually made into a single object. According to electric information in each of the objects, i.e., the virtually unified single object and the other objects excluding the virtually unified single object, objects having the common electric information are connected by straight lines. According to the straight lines, a figure connecting the objects is inputted. A condition for connecting the objects in the figure is inputted. According to the condition, circuit parts are built and signal information is set in a terminal of the circuit parts.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: February 11, 2014
    Assignee: Zuken Inc.
    Inventor: Satoshi Nakamura
  • Publication number: 20140040853
    Abstract: A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.
    Type: Application
    Filed: October 2, 2013
    Publication date: February 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Andreas Tschmelitsch, Gerhard Zojer, Guenter Holl, Guentr Herzele
  • Patent number: 8645898
    Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Mete Erturk, Robert A. Groves, Zhong-Xiang He, Peter J. Lindgren, Anthony K. Stamper
  • Patent number: RE45110
    Abstract: A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 2, 2014
    Inventors: Raminda Udaya Madurawe, Peter Ramyalal Suaris, Thomas Henry White