System-on-chip Design Patents (Class 716/138)
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Patent number: 8745557Abstract: A system and method optimizes hardware description code generated from a graphical program or model automatically. The system may include a streaming optimizer, and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The streaming optimizer may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.Type: GrantFiled: December 8, 2010Date of Patent: June 3, 2014Assignee: The MathWorks, Inc.Inventors: Girish Venkataramani, Kiran Kintali, Pieter J. Mosterman
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Patent number: 8713504Abstract: A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This substitution may occur permanently or temporarily. When an ASIC block is temporarily substituted, faulty outputs of the ASIC block are disabled just at the time they would otherwise propagate an error. The operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed programmable logic. Thus, a fault-infected ASIC block that operates improperly 1% of the time can continue to be gainfully used for the 99% of the time when its operations are fault free. This substitution can be activated in various stages of the ASIC block's life including after: initial design; pilot production; and mass production. This provides for cost saving and faster time-to-market, repair, and maintenance even years after installation and use.Type: GrantFiled: December 24, 2012Date of Patent: April 29, 2014Assignee: Sheyu Group, LLCInventor: James T. Koo
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Patent number: 8689160Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.Type: GrantFiled: June 17, 2013Date of Patent: April 1, 2014Assignee: Industrial Technology Research InstituteInventors: Chang Tzu Lin, Ding Ming Kwai
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Patent number: 8683412Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.Type: GrantFiled: December 23, 2010Date of Patent: March 25, 2014Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Miles P. McGowan
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Patent number: 8677298Abstract: A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify critical and near-critical cyclic logic paths within the user logic design, applying timing optimizations to the critical and near-critical cyclic logic paths, and retiming logic paths other than the critical and near-critical cyclic logic paths.Type: GrantFiled: January 4, 2013Date of Patent: March 18, 2014Assignee: Altera CorporationInventors: Valavan Manohararajah, David Lewis, David Galloway, Ryan Fung
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Patent number: 8664974Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.Type: GrantFiled: January 21, 2011Date of Patent: March 4, 2014Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Patent number: 8667446Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: March 29, 2010Date of Patent: March 4, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Patent number: 8661402Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.Type: GrantFiled: April 4, 2012Date of Patent: February 25, 2014Assignee: Cadence Design Systems, Inc.Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Patent number: 8661399Abstract: Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.Type: GrantFiled: August 6, 2012Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Craig M. Monroe, Michael R. Ouellette, Douglas E. Sprague
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Patent number: 8661400Abstract: A graphical user interface for tuning a programmable device comprises a first on-screen window comprising a representation of a target apparatus, wherein the target apparatus comprises the programmable device, and a second on-screen window configured to appear in response to a selection of a graphical element associated with the representation of the target apparatus, wherein the second on-screen window comprises graphical user interface (GUI) display elements representing a plurality of parameter values presently controlling operation of a device corresponding to the selected graphical element. The second on-screen window is further configured to accept a modification of at least one of the plurality of parameter values via the GUI display elements, initiate communication of the modification to the programmable device, and in response to implementing the modification in the programmable device, display operational results of the device as modified by the modification.Type: GrantFiled: August 15, 2012Date of Patent: February 25, 2014Assignee: Cypress Semiconductor CorporationInventors: Kenneth Y. Ogami, Marat Zhaksilikov, Andrew Best
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Patent number: 8656325Abstract: Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.Type: GrantFiled: January 12, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: John E. Barwin, Amol A. Joshi, Baozhen Li, Michael R. Ouellette
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Patent number: 8650528Abstract: It is possible to improve workability of a design work by handling electric information between one object and other objects associated with the object. A plurality of objects are inputted and electric information is inputted to the objects. Among the objects, mutually connected objects are virtually made into a single object. According to electric information in each of the objects, i.e., the virtually unified single object and the other objects excluding the virtually unified single object, objects having the common electric information are connected by straight lines. According to the straight lines, a figure connecting the objects is inputted. A condition for connecting the objects in the figure is inputted. According to the condition, circuit parts are built and signal information is set in a terminal of the circuit parts.Type: GrantFiled: April 18, 2012Date of Patent: February 11, 2014Assignee: Zuken Inc.Inventor: Satoshi Nakamura
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Publication number: 20140040853Abstract: A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.Type: ApplicationFiled: October 2, 2013Publication date: February 6, 2014Applicant: Infineon Technologies AGInventors: Andreas Tschmelitsch, Gerhard Zojer, Guenter Holl, Guentr Herzele
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Patent number: 8645886Abstract: A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.Type: GrantFiled: April 16, 2012Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Kumar Abhishek, Benjamin J. Ehlers, Sunny Gupta, Stefano Pietri
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Patent number: 8645898Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.Type: GrantFiled: June 28, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Hanyi Ding, Mete Erturk, Robert A. Groves, Zhong-Xiang He, Peter J. Lindgren, Anthony K. Stamper
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Patent number: 8645900Abstract: The invention relates to a method for influencing the selection of a type and form of a circuit implementation in at least one layer in a given integration task for at least one integrated circuit in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. In one embodiment, a plurality of electric or electronic components are spatially arranged and to be electrically connected. Completed solutions x are stored in a database, and each of the completed solutions includes properties for the given integration task. The completed solutions define a destination space from which a solution is selectable by operating elements and determines a type and form of circuit implementation as a result of the given integration task, and aggregates the plurality of electric and electronic components in one of a plurality of integration technologies.Type: GrantFiled: May 7, 2008Date of Patent: February 4, 2014Assignees: Fraunhoffer-Gesellschaft zur Foerderung der Angewandten Forschung E.V., Technische Universitaet BerlinInventors: Michael Schroeder, Karl-Heinz Kuefer, Dmitry-David Polityko
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Patent number: 8640074Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.Type: GrantFiled: November 17, 2011Date of Patent: January 28, 2014Assignee: Mediatek Inc.Inventors: Shen-Yu Huang, Chih-Ching Lin
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Power control using global control signal to selected circuitry in a programmable integrated circuit
Patent number: 8633730Abstract: When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.Type: GrantFiled: August 17, 2012Date of Patent: January 21, 2014Assignee: Xilinx, Inc.Inventors: Chen W. Tseng, Weiguang Lu, William W. Stiehl, Robert M. Balzli, Jr., Carl M. Stern, Aditya Chaubal, Derrick S. Woods -
Patent number: 8634440Abstract: An integrated circuit including multiple instances of identical processing circuitry may be modelled within a field programmable gate array integrated circuit by second processing circuitry connected via a multiplexer to first processing circuitry and operating at a multiple of the clock frequency of the first processing circuitry. Demultiplexing circuitry is used to reform the multiple outputs of the respective separate instances to be fed back to the first processing circuitry.Type: GrantFiled: August 23, 2010Date of Patent: January 21, 2014Assignee: ARM LimitedInventors: Spencer J Saunders, Liam Dillon, Rafal J Janta
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Publication number: 20140017844Abstract: Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Felix P. ANDERSON, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 8631383Abstract: An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output.Type: GrantFiled: June 30, 2008Date of Patent: January 14, 2014Assignee: Qimonda AGInventor: Michael Wagner
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Patent number: 8607174Abstract: A plurality of FPGAs and off-chip storage devices provide a verification module for functionally debugging electronic circuit designs. Signal value compression circuits embedded in each FPGA conserve the limited number of pins available on each FPGA. Transmitting addresses to signal values previously stored in off-chip storage further reduce the bottlenecks in analyzing logic functionality distributed across multiple FPGAs.Type: GrantFiled: July 8, 2012Date of Patent: December 10, 2013Assignee: S2C Inc.Inventor: Mon-Ren Chene
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Patent number: 8601421Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.Type: GrantFiled: October 16, 2009Date of Patent: December 3, 2013Assignee: Lockheed Martin CorporationInventors: Gene D. Tener, Mark A. Goodnough, Jennifer K. Park, David W. Borowski
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Patent number: 8595672Abstract: The invention relates to methods and devices to define and control the design of a configurable chip module, instrument or systems, for example, for measurement, control and communication systems or any portion thereof. The module may include one or more chip elements. This can be achieved using, for example, a Graphical User interface (GUI), that transforms selections made by the user to a hardware and/or software configuration for the system in a process transparent to the user. This enables implementation of a plurality of devices and larger subsystems on a chip or chip module without specific semiconductor design knowledge from the user. This transformation process is thus accomplished transparently to the user, who operates the GUI to define the measurement or action which needs to be performed thereby resulting in an automatic combination of hardware and/or software elements available to create a specific configuration.Type: GrantFiled: June 2, 2011Date of Patent: November 26, 2013Assignee: Innovations Holdings, L.L.C.Inventor: Ewa Herbst
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Patent number: 8582709Abstract: Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.Type: GrantFiled: October 1, 2010Date of Patent: November 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jaegeun Yun, Hyunuk Jung, Junhyung Um, Sunghoon Shim, Sung-Min Hong, Bub-chul Jeong
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Patent number: 8584077Abstract: A method for operating a computer system to generate a layout of a device and a computer-readable medium containing instructions that cause a computer system to carry out that method are disclosed. The computer system has a display that includes a display area. The computer system provides a list of objects and creates user selected objects from the list for inclusion in the display area. The computer assigns one of a plurality of operating modes for each connectivity object in the layout. The computer generates a Net assignment for each connectivity object that is not forced to have a specific Net assignment and for which automatic assignment of a Net is allowed. The computer generated assignment depends on the operating mode associated with that connectivity object. The operating mode of at least one of the connectivity objects can be altered by input from a user of said computer system.Type: GrantFiled: July 30, 2012Date of Patent: November 12, 2013Assignee: Agilent Technologies, Inc.Inventors: Arbind Kumar, John Robert Lefebvre, II, Krishna Kumar Banka, Peter Niday
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Patent number: 8581626Abstract: According to an embodiment, a control system has: a logic module substrate that has a logic FPGA on which logic is mounted, a transmission module that transmits an output logic state signal, which is logic state signal representing an interim logic state of a process by the logic FPGA of deriving a logic output signal from the logic input signals, and a logic monitoring device that displays to monitor the logic state signal transmitted from the transmission module. The logic module substrate includes an event detection unit that detects a change in the logic state signal. Only when a change in the logic state signals is detected by the event detection unit, the logic output state signal being transmitted to the transmission module.Type: GrantFiled: August 25, 2011Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Asakura, Hiroshi Nagahisa, Hidemitsu Hohki, Atsushi Takahashi, Yukitaka Yoshida, Yuji Ichioka, Mamoru Kato
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Patent number: 8578309Abstract: A system and method is disclosed for functional verification and/or simulation of dies in a multi-die 3D ICs. The system and method include converting an I/O trace, embodied as a Value Change Dump, to one or more Universal Verification Methodology objects. This conversion aids in identify and fixing issues contained in die.Type: GrantFiled: January 31, 2012Date of Patent: November 5, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ashok Mehta, Stanley John, Sandeep Kumar Goel, Kai-Yuan Ting
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Patent number: 8572543Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.Type: GrantFiled: April 9, 2012Date of Patent: October 29, 2013Assignee: LSI CorporationInventors: Juergen Dirks, Matthias Dinter, Ralf Leuchter
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Patent number: 8560980Abstract: At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.Type: GrantFiled: November 16, 2010Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Jinjun Xiong, Vladimir Zolotov
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Patent number: 8561001Abstract: Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.Type: GrantFiled: July 11, 2012Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sandeep Kumar Goel
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Patent number: 8549463Abstract: A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing memory mapped control registers associated with the bus subsystems of the supplemental portion of the processing system.Type: GrantFiled: September 29, 2011Date of Patent: October 1, 2013Assignee: Texas Instruments IncorporatedInventor: Agarwala Sanjive
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Patent number: 8543959Abstract: A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a 3D performance determinant is activated in the first candidate chip. A value of a performance parameter is measured for a set of operating conditions. A stacked performance value is computed for the first candidate chip using the value. A subset of the set of candidate chips is stacked in a stack, the subset including the first candidate chip, such that a combined value of the performance parameter for the subset when stacked in a first order is within a defined range of values for the performance parameter.Type: GrantFiled: April 15, 2011Date of Patent: September 24, 2013
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Patent number: 8539398Abstract: A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.Type: GrantFiled: May 27, 2010Date of Patent: September 17, 2013Assignee: Cypress Semiconductor CorporationInventors: John McDonald, Jon Pearson, Kenneth Ogami, Doug Anderson
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Patent number: 8533642Abstract: An automatic code generation application is used to automatically generate code and build programs from a textual model or graphical model for implementation on the computational platform based on the design. One or more model elements may be capable of frame-based data processing. Various options and optimizations are used to generate Hardware Description Language (HDL) code for the frame-based model elements.Type: GrantFiled: January 18, 2011Date of Patent: September 10, 2013Assignee: The MathWorks, Inc.Inventors: Brian K. Ogilvie, Pieter J. Mosterman
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Patent number: 8522188Abstract: In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.Type: GrantFiled: September 25, 2012Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Ock Kim, Jae-Han Jeon, Jung-Yun Choi, Kee-Sup Kim, Hyo-Sig Won
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Patent number: 8522189Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.Type: GrantFiled: March 9, 2011Date of Patent: August 27, 2013Assignee: Intel CorporationInventors: Srinivas Patil, Abhijit Jas
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Patent number: 8522177Abstract: A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level, respectively. A stimulus transaction is generated at a first testbench at the first level. The stimulus transaction is transmitted from the first testbench to a second testbench at the second level. The stimulus transaction is transformed into a first response transaction, using the first model, at the first level. The stimulus transaction received at the second testbench is transformed into a second response transaction, using the second model, at the second level. Functionality of the SoC at the first and second levels is verified based on the first and second response transactions.Type: GrantFiled: November 14, 2012Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Ashok Mehta
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Patent number: 8516433Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.Type: GrantFiled: June 25, 2010Date of Patent: August 20, 2013Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Miles P McGowan
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Patent number: 8510702Abstract: An automated system, and method of operating the same, for interactively routing interconnections in a layout of an integrated circuit. Interconnections among subchips in the integrated circuit, specified by a netlist, are displayed by the system by way of airlines. The system provides a symbolic view of the bus, showing a representative wire of the bus, such as that associated with the least-significant or most-significant bit position in the bus. The physical routing of the representative wire is interactively defined, using orthogonal wire segments in selected conductor levels. Bus properties, for example including bit pitch, wire pitch, LSB/MSB, and a direction of expansion, are associated with the routing data for each segment of the representative wire. The combination of the routing data and the bus property data enable building of the entire bus from the interactive routing of the representative wire in the symbolic view.Type: GrantFiled: November 15, 2011Date of Patent: August 13, 2013Assignee: Texas Instruments IncorporatedInventor: Patrick W. Bosshart
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Patent number: 8504950Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.Type: GrantFiled: July 23, 2010Date of Patent: August 6, 2013Assignee: Otrsotech, Limited Liability CompanyInventor: Eric Dellinger
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Patent number: 8495556Abstract: A system is disclosed for displaying circuitry interconnections as flightlines between a component specified as the local component and the foreign components connecting to the local component. Upon obtaining data of the circuit components and interconnections, a user can designate the local component from among all of the circuit components. The system determines the foreign components connected to that local component, retrieves the flightline appearance display settings for the computer display, and renders a view of the specified local component and its foreign components with flightlines representing each interconnection connection. The flightlines can be color coded to indicate inputs, outputs or other characteristics of interest to the user.Type: GrantFiled: November 9, 2010Date of Patent: July 23, 2013Assignee: Chipworks Inc.Inventor: Michael Green
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Patent number: 8484608Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.Type: GrantFiled: October 9, 2009Date of Patent: July 9, 2013Assignee: LSI CorporationInventors: Gary S. Delp, George Wayne Nation
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Patent number: 8468005Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.Type: GrantFiled: August 12, 2010Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Thomas W. Aarts, Ched D. Hays, Michael C. Hollinger, Jason S. Ma, Jose L. Ortiz, Gundam Raghuswamyreddy
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Patent number: 8453095Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.Type: GrantFiled: July 6, 2011Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang
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Patent number: 8443335Abstract: A word processing or spreadsheet application is augmented by a plug-in and templates for computer aided design of electronic hardware entities. The plug-in utilizes the application programming interface to provide a menu system and executable code which inserts templates, reads and validates data entered into the template, computes addresses, annotates addresses and error messages back to a word processing document for display in the editor of the word processing document, and upon selection and request, generates output files for target simulators or synthesis tools.Type: GrantFiled: May 26, 2012Date of Patent: May 14, 2013Assignee: Agnisys, Inc.Inventor: Anupam Bakshi
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Patent number: 8438523Abstract: In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus.Type: GrantFiled: May 27, 2011Date of Patent: May 7, 2013Assignee: Panasonic CorporationInventors: Daisuke Iwahashi, Masayoshi Tojima, Tokuzo Kiyohara
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Patent number: 8438521Abstract: Methods and apparatus are provided for efficiently implementing an application specific processor. An application specific processor includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A tool uses the selected function units and interconnection information to provide data for implementing the application specific processor. Missing function units or interconnections can be identified and corrected.Type: GrantFiled: May 30, 2008Date of Patent: May 7, 2013Assignee: Altera CorporationInventors: Robert Jackson, Steven Perry
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Patent number: 8417984Abstract: A system for dynamically scaling a power voltage including a system on chip (SoC) and a power control circuit. The SoC includes a plurality of application circuits. The SoC is configured to generate internal clock signals in response to an externally supplied clock signal. The SoC also generates a target voltage that changes based on a change of an operating current. The internal clock signals are respectively provided to the application circuits. The operating current is a sum or total current of the application circuits. The power control circuit generates an internal power voltage based on the target voltage and provides the internal power voltage to the SoC. The system for dynamically scaling a power voltage including a SoC may decrease power consumed in the SoC because the system of dynamically scaling a power voltage decreases a required voltage margin by changing a target voltage before a transition of the SoC current.Type: GrantFiled: September 22, 2011Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Jong Pil Lee
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Patent number: 8407660Abstract: The connection architecture of a network on a chip (NoC) is described in which (a) nodes in octahedron sections are connected in an arc Benes network, (b) a hierarchy of node clusters are connected using a globally asynchronous locally asynchronous (GALA) configuration, (c) a double wishbone 2D torus ring is applied to connection between network layers and (d) data is routed using buffer modulation.Type: GrantFiled: September 12, 2008Date of Patent: March 26, 2013Inventor: Neal Solomon