Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Abstract: Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.

Abstract: An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable function circuits are either interconnected to each other or connected to a plurality of output connectors to transmit manipulated output data signals to external circuitry. The electrically programmable multiple selectable function integrated circuit module has at least one configuration connector, which may be multiplexed with input control and timing signals, connected to a function configuration circuit to receive electrical configuration signals indicating the activation of a program mode and which of the optionally selectable function circuits are to be elected to manipulate the input data signals.

Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.

Abstract: An optimum target system is designed by implementing software modules and hardware modules, without discriminating between the software modules and the hardware modules. An external storage stores the software modules including namespace identifiers for identifying the software modules, and the hardware modules including namespace identifiers for identifying the hardware modules. A module selector specifies a process of a target system to be built, and selects the software modules and the hardware modules that execute the specified process. A namespace manager acquires the namespace identifiers for identifying the software modules, and the namespace identifiers for identifying the hardware modules. A module mapping processor implements either one of the software modules and the hardware modules in the target system, based on the namespace identifiers.

Abstract: Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout of the mother IC includes at least one interface tile having an electrical configuration for communicating with interface logic of the daughter IC. The method includes: obtaining design rules for through die vias (TDVs) to be formed in the mother IC for implementing connections between the at least one interface tile and a physical interface of the daughter IC; defining a layout of the TDVs in the mother IC according to the design rules; and defining at least one mask for programming interconnect on the mother IC to physically connect the TDVs between the at least one interface tile and the physical interface of the daughter IC without changing the electrical configuration of the at least one interface tile.

Abstract: In an initial stage of device design, a circuit analysis control unit of an evaluation board stores SSO noise basic characteristic data actually measured by the evaluation board in an SSO noise basic characteristic data storage unit, and an SSO noise calculation unit calculates a rough amount of SSO noise on the basis of the SSO noise basic characteristic data. After a noise check is OR, the design proceeds, and a PCB parameter is determined, a circuit analysis control unit acquires the SSO noise basic characteristic data according to actual device PCB design information, and corrects the SSO noise basic characteristic data in the SSO noise basic characteristic data storage unit. Then, the SSO noise calculation unit performs a detailed analysis of an amount of SSO noise using the corrected SSO noise basic characteristic data.

Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.

Abstract: The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) used to effect continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability.

Abstract: A system for dynamically scaling a power voltage including a system on chip (SoC) and a power control circuit. The SoC includes a plurality of application circuits. The SoC is configured to generate internal clock signals in response to an externally supplied clock signal. The SoC also generates a target voltage that changes based on a change of an operating current. The internal clock signals are respectively provided to the application circuits. The operating current is a sum or total current of the application circuits. The power control circuit generates an internal power voltage based on the target voltage and provides the internal power voltage to the SoC. The system for dynamically scaling a power voltage including a SoC may decrease power consumed in the SoC because the system of dynamically scaling a power voltage decreases a required voltage margin by changing a target voltage before a transition of the SoC current.

Abstract: The invention relates to multi-planar memory components in a three-dimensional integrated circuit system configuration. A multi-planar memory system consisting of a plurality of memory circuit planes in a three-dimensional system on a chip (3D SoC) comprised of a plurality of memory layers, at least one logic circuit layer and an interface configured to provide access to memory and logic circuit layers.

Abstract: A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically conn

Abstract: Disclosed herein is a device A device of the microelectrode array architecture, comprising: (a) a bottom plate comprising an array of multiple microelectrodes disposed on a top surface of a substrate covered by a dielectric layer; wherein each of the microelectrode is coupled to at least one grounding elements of a grounding mechanism, wherein a hydrophobic layer is disposed on the top of the dielectric layer and the grounding elements to make hydrophobic surfaces with the droplets; (b) a field programmability mechanism for programming a group of configured-electrodes to generate microfluidic components and layouts with selected shapes and sizes; and, (c) a system management unit, comprising: (i) a droplet manipulation unit; and (ii) a system control unit.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the

Abstract: More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands.

Abstract: An apparatus that evaluates a layout of a semiconductor integrated circuit by estimating a result of planarization in manufacturing the circuit includes a unit that divides the layout into partial areas, a unit that calculates, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data, a unit that sets ranges of the wiring density, the total perimeter length, and the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on an equation corresponding to a type of the layout, and a unit that plots the critical regions and the partial area data on a same map.

Abstract: Mechanisms are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SoC under test. The SoC under test generates actual test results data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.

Abstract: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.

Abstract: Method, apparatus, and computer readable medium for implementing a circuit model in an integrated circuit are described. In some examples, the circuit model includes a communication channel between actors. Data portions of at least one data object passed between the actors over the communication channel are identified. An implementation is generated for the circuit model in which data portions are assigned to either local queue storage of the communication channel or centralized shared storage of the communication channel based on levels of access thereof by the actors.

Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

Abstract: One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value.

Abstract: A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.

Abstract: A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.

Abstract: A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Abstract: A user may optimize a circuit design using a control presented within an Internet browser. The user can change the optimization value of the circuit that in turn places more or less emphasis on a parameter (e.g. foot print vs. efficiency). Once optimized for the values, the list of components matching the design as well as the optimization operating values are presented to the user.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Abstract: A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: A system and method of testing IP cores contained in a system-on-chip integrated circuit is disclosed. An operation command is received on an input/output port of the circuit. The operation command includes an operation code component, data component(s), and expected time component. The received operation command is processed to supply test data to each of the IP cores being tested. Result data is received in response to the supplied test data from each of the IP cores being tested. The result data is processed and from the processed result data is generated a status data packet. The status data packet includes the operation code component and a status flag component and is provided on the input/output port.

Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

Abstract: A configurable semiconductor chip module system has analog elements, digital elements, and connection elements between the analog and digital elements. Ones of the analog and digital elements receive inputs from respective sources, and ones of said analog and digital elements output signals for generating control signals having selected electrical and time spatial properties. The connection elements are configurable after creation of the analog elements, the digital elements, and the connection elements.

Abstract: A system-on-a-chip (SoC) to process digital audio-video content includes one or more input/output (I/O) interfaces to transmit the digital audio-video content to corresponding I/O devices coupled to the SoC and to receive the digital audio-video content from the corresponding I/O devices. The SoC also includes a cryptographic engine to encrypt the digital audio-video content being transmitted via the I/O interfaces to the corresponding I/O devices and to decrypt the digital audio-video content received via the I/O interfaces from the corresponding I/O devices.

Abstract: A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Abstract: An automatic system for providing printed circuit board (PCB) layout of a PCB includes an input device, a data processing device, and a storage device. The data processing device includes an invoking module, a calculating module, and a determining module. The invoking module is to read a name and a thickness of each layer of the PCB from the storage device. The calculating module is to calculate an actual length of a via stub of each layer according to the name and thickness of each layer, and calculate an ideal length of the via stub of the PCB according to input information from the input device, and a preset formula. The determining module is to compare the ideal length and the actual length of the via stub of each layer to determine whether the layer can be used as a high-speed signal layout layer or not.

Abstract: Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

Abstract: Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.

Abstract: A semiconductor integrated circuit comprising: a clock gating cell to which an enable signal and a clock signal are input, so as to output a gated clock signal generated by output-controlling said clock signal according to said enable signal; a first flip-flop circuit to which a first input data signal and said gated clock signal are input, so as to retain and output said first input data signal as a first output data signal in synchronization with said gated clock signal; and a second flip-flop circuit to which a second input data signal is input, so as to retain and output said second input data signal as a second output data signal in synchronization with said clock signal if the logical values of said second input data signal and said second output data signal differ from each other, or so as to retain said second output data signal if the logical values of said second input data signal and said second output data signal are the same.