Abstract: In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

Abstract: A present ASIC may include functionality exceeding that which will be operative at one given time (e.g., when the chip is packaged and inserted into a broader circuit). The excess ASIC functionality may be chosen in anticipation of changing market environments, and/or differing product requirements in various market spaces (e.g., in different countries where different interoperability standards are chosen). In such cases, an appropriate subset of the excessive ASIC functionality may be programmably activated for each market space after manufacture.

Abstract: The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.

Abstract: Disclosed is a development support apparatus of a semiconductor device that makes it possible to easily develop the semiconductor device, a development support method, and a program product. A design evaluation apparatus is a design evaluation apparatus having an analog front-end unit for inputting a measurement signal of a sensor and an MCU unit, which has a GUI processing unit for displaying a GUI corresponding to a circuit configuration of the analog front-end unit and a register setting unit that generates setting information for setting up the circuit configuration and a circuit characteristic of the analog front-end unit based on an operation of the GUI by a user, and sets the generated setting information in the analog front-end unit through the MCU unit.

Abstract: A selectable block in a graphical user interface of an electric design automation tool for generating a design of a system on a target device includes a token passing unit operable to pass a token through one of a first output port and second output port in response to a result from a loop test. The selectable block also includes a counter operable to increment a step value in response to the selectable block receiving the token at a first input port.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be incrementally designed and evaluated through structural parameters defined in a schematic diagram data abstraction without modifying and evaluating a layout data abstraction of the circuit directly.

Abstract: A design support apparatus includes a detecting unit, a determining unit, and an inserting unit. The detecting unit detects a via that connects wirings in a circuit to be designed that is expressed by layout information. The determining unit determines the connection position of a dummy via that does not connect wirings, to be on at least one of wirings connected to the via detected by the detecting unit. The inserting unit inserts the dummy via at the connection position determined by the determining unit.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: Methods and systems are provided for analyzing cells of a cell library used to generate a layout. One exemplary method involves determining a routed connection location utilized in the layout for a pin of the cell for each instance of the cell in the layout. The method continues by determining a utilization metric for the pin of the cell based on the plurality of routed connection locations and a plurality of possible connection locations for the pin, and displaying the utilization metric on a display device.

Abstract: The present disclosure relates to a computer-implemented method for electronic design visualization. The method may include providing, using at least one computing device, an electronic design and identifying a plurality of power domains associated with the electronic design. The method may further include associating, using the at least one computing device, at least two of the plurality of power domains with a particular group and displaying one or more of the plurality of power domains in a hierarchical manner.

Abstract: A method for selecting and placing of an IP block in a SOC design based on a topology and/or a density of the SOC design is disclosed. Embodiments include: displaying a user interface; causing, at least in part, a presentation in the user interface of a topology and density view of a SOC design that includes an IP block; and modifying, prior to a tape-out of the SOC design, topology and/or density transition for the IP block in the SOC design based on the presentation.

Abstract: Systems and methods are provided to optimize critical paths by modulating systemic process variations, such as regional timing variations in IC designs. A method includes determining a physical location of an element in the semiconductor chip design within the critical path. The method further includes modulating a systemic process variation of the semiconductor chip design to speed up the critical path based on a polysilicon conductor perimeter density associated with the element.

Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal.

Abstract: A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory.

Abstract: A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Abstract: Aspects of the present disclosure are directed toward methods and systems which generate a plurality of Read-Only Memory (ROM) codes. In response to generating the ROM codes, an image is generated for each of the plurality of ROM codes. The images for each of the plurality of ROM codes are mapped on a single reticle, and a wafer is provided, which includes a plurality of individual devices. The reticle is utilized, which includes an image for each of the plurality of ROM codes, to print a respective one of the images onto a respective one of the plurality of individual devices.

Abstract: The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first retrieve information about an electrical failure from an IC's electrical test result and then identify a set of electrical elements from the IC's layout design including a start resource and an end resource. Next, the method and system identify a physical signal path between the start resource and the end resource using the IC's layout design. Finally, the method and system examine a corresponding region on the semiconductor die that covers the physical signal path for manufacturing defects that may be responsible for the electrical failure.

Abstract: A method of designing a wiring harness using a wiring harness design tool can include allowing a first user to access and edit a first wiring harness design component in a wiring harness design workspace, allowing a second user to access and edit a second wiring harness design component in the wiring harness design workspace at least during a portion of the time that the first user is allowed to access and edit the first wiring harness design component, and displaying the first and second wiring harness design components to the first and second users during at least a portion of the time that access is allowed to the first and second users.

Abstract: A device includes a processor and a computer-readable medium including computer-readable instructions. Upon execution by the processor, the computer-readable instructions cause the device to receive a first request from a second device, where the first request is a layout request that includes an identification of a space. The computer-readable instructions also cause the device to provide a second request to a third device, where the second request includes the identification of the space. The computer-readable instructions also cause the device to receive one or more dimension corresponding to the space, and to provide the one or more dimension to the third device. The computer-readable instructions further cause the device to receive a generated layout from the third device, and to provide the generated layout to the second device.

Abstract: A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and (2) an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters.

Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: A method enables a user to create, edit, monitor and/or optimize the overall machine process of a programmable machine or system assisted by a graphics editor. The programmable machine or system is initially put together as a system of individual machine units which are involved in the overall machine process during certain times by running a number of partial machine processes that are firstly synchronized with one another once they have been set up and then parameters are set for them. These method steps take place in a two-dimensional process diagram created by the graphics editor that plots all the partial machine processes involved in the overall machine process via assigned process symbols that are positioned or repositioned by the graphics editor so that they are arranged in a machine component dimension and in a time dimension.

Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: A global placer receives a plurality of regions, each region occupying a sub-area of a design area. receives a plurality of movebound objects, each movebound object associated with a region. The global placer receives a plurality of unconstrained objects, each unconstrained object associated with no region. The global placer receives a tolerance, wherein the placement tolerance defines a coronal fringe to at least one region. The global placer initially placing the plurality of movebound objects and unconstrained objects. The global placer iterates over objects without preference to region-affiliation to select an object, wherein the objects are comprised of the plurality of movebound objects and plurality of unconstrained objects. The global placer determines whether movebound object is within the tolerance of a region associated with the movebound object.

Abstract: Disclosed are improved methods, systems, and computer program products for visualizing and estimating IC die arrangement for an electronic design, and for performing chip planning and estimation based upon the estimated and visualized IC die arrangements. According to some approaches, an interface is provided for visualizing different die arrangement options for an electronic design, in which a filmstrip view is provided to display smaller images of different die arrangement options, and a central viewing area is provided to view a larger image of a selected candidate die arrangement. The different images, whether smaller or larger images, are maintained with design object information and not just static images. This allows for selection and highlighting of individual objects within the die arrangement images, as well as corresponding highlighting of that same object in other images.

Abstract: Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated.

Abstract: Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.

Abstract: Techniques for determining and a computing device configured to determine a quantum Karnaugh map through decomposing a quantum circuit into a multiple number of sub-circuits are provided. Also, techniques for obtaining and a computing device configured to obtain a quantum circuit which includes the minimum number of gates among possible quantum circuits corresponding to a quantum Karnaugh map are also provided.

Abstract: A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan.

Abstract: A verification support program that causes a computer to execute identifying from a finite state machine model related to a circuit-under-test, an input count of transitions to a transition-end state and an output count of transitions from the transition-end state; determining the transition-end state to be a record/restore subject, if the identified output transition is greater than the identified input transition count; embedding record-instruction information causing the record/restore subject to be recorded to a database, if a first element causing transition to the record/restore subject is included in a first test scenario that is in a test scenario group related to the circuit-under-test; and embedding restore-instruction information causing the record-restore subject to be restored from the database, if a second element causing transition to the record-restore subject is included in a series of elements making up a second test scenario that is in the test scenario group.

Abstract: Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.

Abstract: A charged particle beam writing apparatus and a charged particle beam writing method capable of shortening the time necessary to generate shot data and improving writing throughput. A graphic pattern defined in write data is divided into graphics represented in shot units. The divided graphics are temporarily stored in a memory and are distributed to their corresponding subfield areas while developing position information defined in a state of being compressed to write data. When each pattern is written by multi-pass writing, graphics divided at a first pass are used for distribution to subfield areas after a second pass.

Abstract: The apparatus of the present invention includes a block diagram dividing unit that divides a block diagram into a plurality of pieces at a branch point, connects a branch point block element to one end of a data line which has been connected to the branch point at each divided piece and thereby generates a plurality of block diagram pieces, a program instruction generator that generates program instructions for performing processing on each block diagram piece, an execution sequence determining unit that determines an execution sequence of generated program instructions, a structural information generator that generates structural information of each of the block diagram pieces and a program generator that arranges the program instructions according to the execution sequence, writes structural information of each block diagram piece into a comment line of each of the program instructions corresponding to each of the block diagram pieces and thereby generates a program.

Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

Abstract: A system or technique provides for a hierarchical visual-based analysis of electrical integrated circuit system simulation results. A 3D visualization may be used to identify and conduct an analysis of the integrated circuit. An analysis is done on a specific feature of the integrated circuit that is visible in the 3D visualization. The specific feature may be one that is obscured by other layers of the integrated circuit visualization.

Abstract: A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format.

Abstract: A graphical user interface for tuning a programmable device comprises a first on-screen window comprising a representation of a target apparatus, wherein the target apparatus comprises the programmable device, and a second on-screen window configured to appear in response to a selection of a graphical element associated with the representation of the target apparatus, wherein the second on-screen window comprises graphical user interface (GUI) display elements representing a plurality of parameter values presently controlling operation of a device corresponding to the selected graphical element. The second on-screen window is further configured to accept a modification of at least one of the plurality of parameter values via the GUI display elements, initiate communication of the modification to the programmable device, and in response to implementing the modification in the programmable device, display operational results of the device as modified by the modification.

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.

Abstract: A design tool provides interactive graphical pin assignment. In one embodiment, the design tool identifies layout restrictions of a configurable processing device that includes a plurality of pins. The design tool further provides an interactive visual representation of a pin assignment that accommodates the layout restrictions and a user input.

Abstract: A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.

Abstract: Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.

Abstract: An automated system, and method of operating the same, for assisting the layout of components and the routing of conductors in a layout of an integrated circuit. An asymmetric zoom command is provided, by way of which the user can magnify the current view of a portion of the layout in one dimension while maintaining the original magnification in the orthogonal dimension. The commands can be conveyed by keystrokes, or by a command in combination with a drawn rectangle indicating the extent of the asymmetric zoom magnification. Both asymmetric zoom-in and asymmetric zoom-out are supported.

Abstract: The invention relates to a method for influencing the selection of a type and form of a circuit implementation in at least one layer in a given integration task for at least one integrated circuit in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. In one embodiment, a plurality of electric or electronic components are spatially arranged and to be electrically connected. Completed solutions x are stored in a database, and each of the completed solutions includes properties for the given integration task. The completed solutions define a destination space from which a solution is selectable by operating elements and determines a type and form of circuit implementation as a result of the given integration task, and aggregates the plurality of electric and electronic components in one of a plurality of integration technologies.