Abstract: A method for compensating an effect of a patterning process is illustrated. The main concept of the method for compensating the effect of the patterning process is to add or subtract the correction amounts for all segments according to the set of the comparison values at the set of the evaluation points. Compared with the delta-chrome optical proximity correction method, the run time of the method for compensating the effect of the patterning process is reduced, the memory usage of the method for compensating the effect of the patterning process not increased, and the correction accuracy of the method for compensating the effect of the patterning process is not reduced.

Abstract: Integrated circuit (IC) methods for optical proximity correction (OPC) modeling and mask repair are described. The methods include use of an optical model that generates a simulated aerial image from an actual aerial image obtained in an optical microscope system. In the OPC modeling methods, OPC according to stage modeling is simulated, and OPC features may be added to a design layout according to the simulating OPC. In the mask repair methods, inverse image rendering is performed on the actual aerial image and diffraction image by applying an optical model that divides an incoherent exposure source into a plurality of coherent sources.

Abstract: A method for predicting pattern critical dimensions in a lithographic exposure process includes defining relationships between critical dimension, defocus, and dose. The method also includes performing at least one exposure run in creating a pattern on a wafer. The method also includes creating a dose map. The method also includes creating a defocus map. The method also includes predicting pattern critical dimensions based on the relationships, the dose map, and the defocus map.

Abstract: In a first process, a process A, an actually measured transfer position measured by a measurement/inspection instrument is indicated by a black circle. A targeted transfer position indicated by x in a process B is located at the same position as the black circle. Assuming that the weights in the subsequent processes are the same, a targeted transfer position Xtarget indicated by x in processes C, D and E is located at a moderate position with which the total deviation from an actual transfer position (black circle) measured by the measurement/inspection instrument in a process preceding the current process is minimized, that is, at a proper position with respect to a plurality of other processes. Accordingly, the productivity of devices can be improved.

Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

Abstract: A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the design rule, as violating patterns, and corresponding violation values, and determining violating patterns having a minimum violation value among the violating patterns. Further, the method includes classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value, and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.

Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments include obtaining qualitative data from within the pattern area of a reticle indicative of the physical characteristics of the pattern area. Additional embodiments include obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. In further embodiments qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. Several embodiments provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements. This is expected to provide accurate data for correcting the photolithography tool to compensate for variances in the pattern area, and to increase throughput because the photolithography tool is not used to measure the reticle.

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Abstract: Targeted production control using multivariate analysis of design marginalities. A list of a plurality of metrology operations is accessed during production of an integrated circuit device. The list is generated from operations performed in the design of the integrated circuit device. At least one of the plurality of metrology operations is performed on the integrated circuit device. A manufacturing process of the integrated circuit device may be adjusted responsive to results of the performing.

Abstract: According to one embodiment, a method for making a correction map of a dose amount of EUV light used when exposing with the EUV light, includes estimating an exposure result based on an initial correction map of the dose amount and flare of the EUV light, determining a goodness of the exposure result, and correcting the initial correction map in the case where the exposure result is unacceptable. And, the correcting of the initial correction map, the estimating of the exposure result, and the determining of the goodness are repeated until the exposure result is good.

Abstract: Described herein are methods and systems for efficiently preparing a wafer layout for processing into a photomask. Portions of layouts containing semiconductor features and designs that are frequently used can be stored in a database. These portions can be post-decomposition, with all treatment and error checking already performed upon them. When a wafer layout is received for processing into a photomask, the processing and decomposition time can be reduced by analyzing the layout, and replacing sections of the layout with the portions from the database that have already been decomposed and processed. As these sections no longer need to be decomposed, error checked, and treated, the processing time is greatly reduced, and photomasks can be made quicker and more efficiently.

Abstract: Disclosed are techniques for simulating and correcting the mask shadowing effect using the domain decomposition method (DDM). According to various implementations of the invention, DDM signals for an extreme ultraviolet (EUV) lithography mask are determined for a plurality of azimuthal angles of illumination. Base on the DDM signals, one or more layout designs for making the mask may be analyzed and/or modified.

Abstract: Implementing circuit tuning post design of an integrated circuit utilizing gate phases. Each phase includes a designation of one of a slow phase and a fast phase. During the circuit design phase, each device is given a phase designation based upon expected performance of the device in the circuit. If the device is expected to be in a critical path or has a minimum timing slack, the device is placed on the fast phase. If the device is not in a critical path or has excess timing slack the device is placed on the slow phase.

Abstract: A method for minimizing errors of a plurality of photolithographic masks that serve for successively processing a substrate is provided. The method includes determining a reference displacement vector field, in which the reference displacement vector field correlates displacement vectors of the errors of the plurality of photolithographic masks. The method includes determining for each of the photolithographic mask a difference displacement vector field as a difference between the reference displacement vector field and the displacement vectors of the errors of the respective photolithographic mask, and correcting the errors for each of the photolithographic masks using the respective difference displacement vector field.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Abstract: A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse patterns if d?5a and c?1.5b or if 5a>d?3a and c?1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided.

Abstract: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction, data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.

Abstract: The present invention includes a computing system determining a best alias rule in a semiconductor manufacturing process. The computing system obtains an original rule and candidate alias rules based on sampled data from the semiconductor manufacturing process. The computing system compares the original rule to the candidate alias rules. The computing system ranks the candidate alias rules according to the comparison. The computing system filters the ranked candidate alias rules. A user selects one rule among the filtered candidate alias rules based on knowledge of the semiconductor manufacturing process.

Abstract: Aspects of the invention relate to retargeting based on process window simulation to fix hotspots. The process window simulation is performed to generate process window information. Edge fragments are selected for retargeting. Based on the process window information, the selected edge fragments are retargeted in a balanced way.

Abstract: Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.

Abstract: A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes of a predetermined size, based on an area density of the each small region, calculating a second dimension correction amount in accordance with a line width dimension of the pattern to be written in the each small region, correcting the first dimension correction amount by using the second dimension correction amount, and resizing the line width dimension of the pattern by using a corrected first dimension correction amount, and outputting a result of the resizing.

Abstract: A semiconductor cell for photomask data verification is disclosed that is provided in a semiconductor chip having a semiconductor integrated circuit and used for verifying photomask data of the semiconductor chip obtained by performing arithmetic processing on layout data of the semiconductor integrated circuit. The semiconductor cell for photomask data verification has the photomask data obtained by performing the arithmetic processing on the layout data of the semiconductor integrated circuit and is electrically separated from the semiconductor integrated circuit.

Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.

Abstract: A method of forming a photomask using a calibration pattern that may exactly transfer a desired pattern to a substrate. The method includes providing one-dimensional calibration design patterns each having first design measures and providing two-dimensional calibration design patterns each having second design measures; obtaining one-dimensional calibration measured patterns using the one-dimensional calibration design patterns and obtaining two-dimensional calibration measured patterns using the two-dimensional calibration design patterns; obtaining first measured measures of the one-dimensional calibration measured patterns and obtaining second measured measures of the two-dimensional calibration measured patterns; establishing a correlation between the first measured measures and the second measured measures; and converting a main measured measure of a main pattern into a corresponding one of the first measured measures using the correlation.

Abstract: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

Abstract: A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Abstract: Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification task in some embodiments. The methods or the systems may further determine or identify an inverse transform and apply the inverse transform to a shape before adding the shape to the hierarchical output. In some embodiments, there exists no duplication among the shapes in the hierarchical output, or only shapes derived from original shapes that belong to the first instance of a cellview master are added to the hierarchical output.

Abstract: According to one embodiment, a flare prediction method in photolithography includes determining a pattern density distribution of a pattern layout, determining an inclination of a variation in the pattern density distribution, and performing a flare calculation in a plurality of partition sizes based on the inclination of a variation in the pattern density distribution.

Abstract: A technique for providing information about defects in a mask pattern is described. In this technique, defects in the mask pattern may be determined based on differences between a calculated pattern produced at an image plane in the photolithographic process, when the mask pattern, illuminated by an associated source pattern, is at an object plane in the photolithographic process, and a target pattern that excludes the defects. Then the defect information may be provided to the user, such as a spatial map of the determined defects, where the spatial map is associated with at least the portion of the mask pattern.

Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Abstract: A method for selecting sample positions on a substrate from a set of all available sample positions is provided, in which a representation of a model, which may represent the variation of one or more properties across the substrate, is analyzed in order to identify the sample positions having the greatest effect on the model.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: Correction of reticle defects, including reticle weak spots or shortcomings, is accomplished with a second exposure. Embodiments include obtaining a reticle with a pattern corresponding to a wafer pattern design, exposing a wafer with the reticle, modifying the design, designating variations between the design and the modified design as reticle defects, and exposing the wafer with correction patterns containing structure corresponding to the modified design at defect positions. Other embodiments include modifying, eliminating, and/or shifting the pattern near a reticle blank defect position, and exposing a wafer with the reticle and with a correction pattern containing structure corresponding to the design at a defect position; modifying a patterned reticle surface layer near a defect forming an expanded defect, exposing a wafer with the modified reticle and with an expanded defect correction pattern; and exposing a wafer with a reticle and with a correction pattern larger than a detected reticle defect.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Abstract: Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques.

Abstract: A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.

Abstract: A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.

Abstract: Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.

Abstract: A library of waivable images with corresponding waiver constraints is generated. Each of the waivable images is an image of a region of a reference design layout including a raw error as determined by an optical rule checks (ORC) program and does not require a correction for printability on a photoresist layer. A list of raw errors is generated by running the ORC program on a target design layout. Error region images corresponding to the list of raw errors are generated by selecting a region of the target design layout around points corresponding to the raw errors. A list of matches between the library of waivable images and the error region images is generated. By removing a subset of raw errors that correspond to a subset of the list of matches from the list of raw errors, a list of real errors is generated.

Abstract: A method of generating a mask having optical proximity correction features.