Abstract: A method and apparatus for printing an electric circuit directly on a target surface having a three-dimensional shape are provided. In this method, a 3D printing apparatus that can be attached to a target surface is used. In this printing method, two-dimensional information about the shape of the electric circuit to be printed and information about the three-dimensional shape of the target surface are input. Two-dimensional information about the shape of the electric circuit to be printed is adjusted based on the information about the three-dimensional shape of the target surface to generate three-dimensional information about the electric circuit to be printed. Based on this, a tool path for controlling the 3D printing apparatus is generated. An electric circuit can be directly fabricated on a target surface having a three-dimensional shape by the method and apparatus.

Abstract: A semiconductor device, includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including a gate structure extending in a first direction and an active region provided on both sides of the gate structure in a second direction intersecting the first direction; and a plurality of interconnection patterns connected to the plurality of semiconductor elements, wherein the plurality of interconnection patterns include a plurality of upper interconnections provided above the plurality of semiconductor elements in a third direction, a plurality of intermediate interconnections provided between the plurality of semiconductor elements and the plurality of upper interconnections in the third direction, and a routing interconnection adjacent to at least one of the plurality of semiconductor elements in the second direction, wherein the routing interconnection is connected to at least one of the plurality of intermediate interconnections in the first direction or the second directio

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Abstract: A method for determining process window limiting patterns based on aberration sensitivity associated with a patterning apparatus. The method includes obtaining (i) a first set of kernels and a second set of kernels associated with an aberration wavefront of the patterning apparatus and (ii) a design layout to be printed on a substrate via the patterning apparatus; and determining, via a process simulation using the design layout, the first set of kernels, and the second set of kernels, an aberration sensitivity map associated with the aberration wavefront, the aberration sensitivity map indicating how sensitive one or more portions of the design layout are to an individual aberrations and an interaction between different aberrations; determining, based on the aberration sensitivity map, the process window limiting pattern associated with the design layout having relatively high sensitivity compared to other portions of the design layout.

Abstract: Multi-purpose interface bumps on semiconductor chips may be used to optimize chip-to-chip data connectivity, including for example high speed chip-to-chip interfaces using fine-pitched bumps adaptable to interfaces with standard bumps without loss of total data rate. A chip with fine-pitch pads for ?-bumps may be connected to an organic package substrate with every other pad populated with a bump and connected to the organic package substrate, while adjacent pads are not populated with bumps and are deactivated. Total number of active bumps to 1/N for each data interface block, and the total bandwidth may be maintained by increasing the active bump data rate by N-times.

Abstract: A method of modeling damages to a crystal caused by an incident particle includes obtaining particle information and crystal information; estimating energy loss of the incident particle based on the particle information and the crystal information; estimating a volume of a vacancy based on the energy loss; estimating a vacancy reaction based on the crystal information and the volume of the vacancy; and generating output data based on the vacancy reaction, the output data including quantification data of the damages.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: A nanofabrication method comprises receiving information regarding in-plane distortion of a substrate, modeling target out-of-plane displacement as a summation of a plurality of geometric modes represented by a linear combination of basis functions, generating a first drop pattern of formable material based on the modeled out-of-plane displacement, generating a second drop pattern by merging the first drop pattern with a drop pattern based on a topography of the template and the substrate; dispensing drops of formable material onto the substrate according to the second drop pattern, and contacting the dispensed drops with the template to form a film. The plurality of geometric modes are modified using a plurality of unique predetermined correction coefficients. Each unique predetermined correction coefficient represents a relationship between an analytically determined amount of in-plane distortion and an empirically determined amount of in-plane distortion.

Abstract: The present disclosure discloses a method of fabricating a semiconductor layout comprising the following steps. A layout is provided, and the layout includes a plurality of connection patterns. The connection patterns are decomposed to a plurality of first connection patterns and a plurality of second connection patterns alternatively arranged with each other. An optical proximity correction process is performed on the first connection patterns and the second connection patterns to form a plurality of third connection patterns and a plurality of fourth connection patterns, wherein at least a portion of the third connection patterns is overlapped with the fourth connection patterns. The third connection patterns and the fourth connection patterns are outputted to form photomasks. Accordingly, the quality of the photomask may be improved, and the photomask may therefore include more accurate patterns and contours. The present disclosure also provides a method of fabricating a semiconductor structure.

Abstract: A method for determining a best focus and a best dose in the disclosure includes selecting a selection pattern from first and second shot regions of a wafer for split, measuring a critical dimension (CD) value of the selection pattern, thereby deriving a measurement CD value, calculating an effective CD value of the selection pattern for each of the first and second shot regions using the measurement CD value, calculating an upper-limit CD value and a lower-limit CD value of the selection pattern using the effective CD value of the selection pattern, calculating a process window area for the first shot region and a process window area for the second shot region using the upper-limit CD value and the lower-limit CD value of the selection pattern, and comparing the process window area for the first shot region and the process window area for the second shot region with each other.

Abstract: A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: An overlay target includes a grating-over-grating structure with a bottom grating structure disposed on a specimen and a top grating structure disposed on the bottom grating structure. The overlay target further includes a calibration scan location including the bottom grating structure but not the top grating structure and an overlay scan location including the top grating structure and the bottom grating structure.

Abstract: Embodiments of the present disclosure relate to in-line detection of electrical fails on integrated circuits. One embodiment is an apparatus including a device region with integrated circuits and a test region for in-line failure detection of the integrated circuits using an in-line voltage contrast test, the apparatus comprising: a substrate including a first area for the device region and a second different area for the test region; metal layers formed over both areas; wherein the integrated circuits are formed from first sections of the layers; and wherein a second section of an upper metal layer of the layers is segmented into test segments, each test segment to exhibit a predefined response during the in-line voltage contrast test depending on whether the test segment is shorted, or not, to the substrate and/or the second section of a gate layer of the layer. Other embodiments may be disclosed and/or claimed.

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: An operating method of an extreme ultraviolet (EUV) lithography device includes defining a target image to render an illumination system, assigning priorities to respective positions of facets of a pupil facet mirror corresponding to the target image, assigning a mirror according to the assigned priorities using linear programming, generating the illumination system by selecting one of the facets of the pupil facet mirror based on a symmetry criterion, and converting mirror assignment information and source map information corresponding to the selected facet into a form recognizable by an EUV scanner.

Abstract: Embodiments disclosed herein include a semiconductor manufacturing tool with a hybrid model and methods of using the hybrid model for processing wafers and/or developing process recipes. In an embodiment, a method for developing a semiconductor manufacturing process recipe comprises selecting one or more device outcomes, and querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes. In an embodiment, the hybrid process model comprises a statistical model and a physical model. In an embodiment, the method may further comprise executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model.

Abstract: A method including obtaining (i) measurements of a parameter of the feature, (ii) data related to a process variable of a patterning process, (iii) a functional behavior of the parameter defined as a function of the process variable based on the measurements of the parameter and the data related to the process variable, (iv) measurements of a failure rate of the feature, and (v) a probability density function of the process variable for a setting of the process variable, converting the probability density function of the process variable to a probability density function of the parameter based on a conversion function, where the conversion function is determined based on the function of the process variable, and determining a parameter limit of the parameter based on the probability density function of the parameter and the measurements of the failure rate.

Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

Abstract: A method for determining a probabilistic model configured to predict a characteristic (e.g., defects, CD, etc.) of a pattern of a substrate subjected to a patterning process. The method includes obtaining a spatial map of a distribution of a residue corresponding to a characteristic of the pattern on the substrate, determining a zone of the spatial map based on a variation of the distribution of the residue within the spatial map, and determining the probabilistic model based on the zone and the distribution of the residue values or the values of the characteristic of the pattern on the substrate within the zone.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.

Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

Abstract: Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.

Abstract: A learning device for performing a machine learning based on a learning model using data input to an input layer, includes: a calculation part configured to calculate a predetermined number of features, in which simulation data as a result of simulating semiconductor manufacturing processes by setting environmental information inside a process vessel in which the semiconductor manufacturing processes are performed and using a predetermined component provided in the process vessel as a variable, and XY coordinates parallel to a plane of a wafer are associated with each other; and an input part configured to input the calculated predetermined number of features to the input layer.

Abstract: A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

Abstract: A method of designing and manufacturing a replica composite object based on an original object. The method identifies the structure and physical properties of an original object. Base materials, bodies, and structural templates, each of which includes associated physical properties, are utilized to generate a 3-dimensional model. The 3-dimensional model is discretized and tested to determine if the selected combination of base materials and bodies have physical properties that substantially equal the physical properties of the original object. If the physical properties do not equate, the 3-dimensional model is optimized by adjusting the combination of base materials, bodies, and structural templates. When the difference between the measured physical properties of the 3-dimensional model and the identified physical properties of the original object is less than a tolerance value, the method instructs an additive manufacturing system to generate a replica composite object based on the original object.

Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

Abstract: The independent claims of this patent signify a concise description of embodiments. An automatic process for determining and/or predicting the original root-cause(s) of a violation is proposed using two major enhancements on top of the current VC-Static solution. First, an information repository is created by mining various Static checker components' analysis information, and second, an analysis framework is created which systematically prunes the above-mentioned information repository to find the actual root cause(s) of the violation. This Abstract is not intended to limit the scope of the claims.

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.

Abstract: Embodiments of techniques for inverse design of physical devices are described herein, in the context of generating designs for photonic integrated circuits (including a multi-channel photonic demultiplexer). In some embodiments, an initial design of the physical device is received, and a plurality of sets of operating conditions for fabrication of the physical device are determined. In some embodiments, the performance of the physical device as fabricated under the sets of operating conditions is simulated, and a total performance loss value is backpropagated to determine a gradient to be used to update the initial design. In some embodiments, instead of simulating fabrication of the physical device under the sets of operating conditions, a robustness loss is determined and combined with the performance loss to determine the gradient.

Abstract: A method of determining candidate patterns from a set of patterns of a patterning process. The method includes obtaining (i) a set of patterns of a patterning process, (ii) a search pattern having a first feature and a second feature, and (iii) a search condition comprising a relative position between the first feature and the second feature of the search pattern; and determining a set of candidate patterns from the set of patterns that satisfies the search condition associated with the first feature and the second feature of the search pattern.

Abstract: The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for Hessian-Free photolithography mask optimization. The method includes steps: S1, inputting a design layout of a mask to be optimized; S2, positioning error monitoring points on the design layout of the mask to be optimized; S3, obtaining an optimization variable x of the mask to be optimized; S4, forming an objective function cost on the optimization variable x; and S5, optimizing the objective junction cost by a Hessian-Free-based conjugate gradient method, to obtain an optimization result of the mask to be optimized. Optimizing the objective function cost based on a Hessian-Free conjugate gradient method to obtain an optimization result of the mask to be optimized, which can greatly reduce the computation resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency.

Abstract: A method for representing a layout of an integrated circuit (IC) includes, in part, determining multiple regions of the IC layout based on one or more parameters, determining multiple areas associated with the multiple regions where each area has a characteristic of a region of the multiple regions, assigning a first set of values to locations of the IC layout outside the multiple areas, assigning a second set of values to locations of the IC layout within the multiple areas, and, in response to a determination that a location of the IC layout is in two or more overlapping areas of the multiple areas, determining a value to assign to the location in accordance with the values of the two or more overlapping areas. The method further includes generating data representative of the IC layout design in accordance with the first and second set of values, and the assigned value.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A method for inspection of a patterning device. The method includes obtaining (i) patterning device apparatus data of a patterning device making process, (ii) a patterning device substrate map based on the patterning device apparatus data, and (iii) predicted process window limiting pattern locations corresponding to the patterning device based on the patterning device substrate map, and based on the process window limiting pattern locations, guiding a patterning device inspection apparatus to the process window limiting pattern locations for defect inspection.

Abstract: The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for photolithographic mask optimization of joint optimization of pattern and image. The method includes steps: inputting the main pattern; dividing edges of each main pattern into short edges, and regarding the short edges as a first variable for optimizing the main pattern; generating same or similar assistant feature sample points around same or similar main patterns, and regarding the assistant feature sample points as a second variable for optimizing the main pattern; and forming an objective function with the first variable and the second variable as optimization variables. The rules for generating assistant feature sample points around each main pattern are consistent, which are not limited to specific locations of the main pattern and ensures the consistency of final results for optimizing each main pattern.

Abstract: A method of determining a sampling control scheme and/or a processing control scheme for substrates processed by a device. The method uses a fingerprint model and an evolution model to generate the control scheme. The fingerprint model is based on fingerprint data for a processing parameter of at least one substrate processed by a device, and the evolution model represents variation of the fingerprint data over time. The fingerprint model and the evolution model are analyzed and a sampling and/or processing control scheme is generated using the analysis. The sampling control scheme provides an indication for where and when to take measurements on substrates processed by the device. The processing control scheme provides an indication for how to control the processing of the substrate. Also, there is provided a method of determining which of multiple devices contributed to a fingerprint of a processing parameter.

Abstract: Systems and methods for calculating a printed area metric indicative of stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, with the resulting stochastic randomness potentially becoming a major challenge. To characterize the stochastic phenomena, a printed area metric may be generated analytically (rather than via simulations) and comprise one or more defined moments for a printed area distribution associated with the printed area that are indicative of one or more aspects associated with printing. For example, the printed area metric may be indicative of the likelihood of printing within the printed area or the variance of printing within the printed area due to stochastic randomness in one or both of exposure or resist process.

Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

Abstract: A method to improve a lithographic process of imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including computing a multi-variable cost function. The multi-variable cost function represents an interlayer characteristic, the interlayer characteristic being a function of a plurality of design variables that represent one or more characteristics of the lithographic process. The method further includes reconfiguring one or more of the characteristics of the lithographic process by adjusting one or more of the design variables and computing the multi-variable cost function with the adjusted one or more design variables, until a certain termination condition is satisfied.