Manufacturing Optimizations Patents (Class 716/54)
  • Patent number: 11366952
    Abstract: The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for Hessian-Free photolithography mask optimization. The method includes steps: S1, inputting a design layout of a mask to be optimized; S2, positioning error monitoring points on the design layout of the mask to be optimized; S3, obtaining an optimization variable x of the mask to be optimized; S4, forming an objective function cost on the optimization variable x; and S5, optimizing the objective junction cost by a Hessian-Free-based conjugate gradient method, to obtain an optimization result of the mask to be optimized. Optimizing the objective function cost based on a Hessian-Free conjugate gradient method to obtain an optimization result of the mask to be optimized, which can greatly reduce the computation resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: June 21, 2022
    Assignee: SHENZHEN JINGYUAN INFORMATION TECHNOLOGY CO., LTD
    Inventor: Ming Ding
  • Patent number: 11361139
    Abstract: A method for representing a layout of an integrated circuit (IC) includes, in part, determining multiple regions of the IC layout based on one or more parameters, determining multiple areas associated with the multiple regions where each area has a characteristic of a region of the multiple regions, assigning a first set of values to locations of the IC layout outside the multiple areas, assigning a second set of values to locations of the IC layout within the multiple areas, and, in response to a determination that a location of the IC layout is in two or more overlapping areas of the multiple areas, determining a value to assign to the location in accordance with the values of the two or more overlapping areas. The method further includes generating data representative of the IC layout design in accordance with the first and second set of values, and the assigned value.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: June 14, 2022
    Assignee: Synopsys, Inc.
    Inventor: Ralph Iverson
  • Patent number: 11354478
    Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: June 7, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lukas Daellenbach, Ralf Richter
  • Patent number: 11287748
    Abstract: A method for inspection of a patterning device. The method includes obtaining (i) patterning device apparatus data of a patterning device making process, (ii) a patterning device substrate map based on the patterning device apparatus data, and (iii) predicted process window limiting pattern locations corresponding to the patterning device based on the patterning device substrate map, and based on the process window limiting pattern locations, guiding a patterning device inspection apparatus to the process window limiting pattern locations for defect inspection.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 29, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Anton Bernhard Van Oosten, Vidya Vaenkatesan, James Norman Wiley, Reinder Teun Plug
  • Patent number: 11281110
    Abstract: A method of determining a sampling control scheme and/or a processing control scheme for substrates processed by a device. The method uses a fingerprint model and an evolution model to generate the control scheme. The fingerprint model is based on fingerprint data for a processing parameter of at least one substrate processed by a device, and the evolution model represents variation of the fingerprint data over time. The fingerprint model and the evolution model are analyzed and a sampling and/or processing control scheme is generated using the analysis. The sampling control scheme provides an indication for where and when to take measurements on substrates processed by the device. The processing control scheme provides an indication for how to control the processing of the substrate. Also, there is provided a method of determining which of multiple devices contributed to a fingerprint of a processing parameter.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 22, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Jeroen Van Dongen, Wim Tjibbo Tel, Sarathi Roy, Yichen Zhang, Andrea Cavalli, Bart Laurens Sjenitzer, Simon Philip Spencer Hastings
  • Patent number: 11281839
    Abstract: The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for photolithographic mask optimization of joint optimization of pattern and image. The method includes steps: inputting the main pattern; dividing edges of each main pattern into short edges, and regarding the short edges as a first variable for optimizing the main pattern; generating same or similar assistant feature sample points around same or similar main patterns, and regarding the assistant feature sample points as a second variable for optimizing the main pattern; and forming an objective function with the first variable and the second variable as optimization variables. The rules for generating assistant feature sample points around each main pattern are consistent, which are not limited to specific locations of the main pattern and ensures the consistency of final results for optimizing each main pattern.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 22, 2022
    Assignee: SHENZHEN JINGYUAN INFORMATION TECHNOLOGY CO., LTD
    Inventors: Ming Ding, Weijie Shi
  • Patent number: 11270054
    Abstract: Systems and methods for calculating a printed area metric indicative of stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, with the resulting stochastic randomness potentially becoming a major challenge. To characterize the stochastic phenomena, a printed area metric may be generated analytically (rather than via simulations) and comprise one or more defined moments for a printed area distribution associated with the printed area that are indicative of one or more aspects associated with printing. For example, the printed area metric may be indicative of the likelihood of printing within the printed area or the variance of printing within the printed area due to stochastic randomness in one or both of exposure or resist process.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 8, 2022
    Assignee: Siemens Industry Software Inc.
    Inventors: Hyejin Jin, John L. Sturtevant, Shumay D. Shang, Azat Latypov, Germain Louis Fenger, Gurdaman Khaira
  • Patent number: 11232249
    Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: January 25, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Quan Zhang, Been-Der Chen, Rafael C. Howell, Jing Su, Yi Zou, Yen-Wen Lu
  • Patent number: 11112700
    Abstract: A method to improve a lithographic process of imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including computing a multi-variable cost function. The multi-variable cost function represents an interlayer characteristic, the interlayer characteristic being a function of a plurality of design variables that represent one or more characteristics of the lithographic process. The method further includes reconfiguring one or more of the characteristics of the lithographic process by adjusting one or more of the design variables and computing the multi-variable cost function with the adjusted one or more design variables, until a certain termination condition is satisfied.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 7, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wim Tjibbo Tel, Laurent Michel Marcel Depre, Jorge Humberto Salvador Entradas
  • Patent number: 11093680
    Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Synopsys, Inc.
    Inventors: Lawrence S. Melvin, III, Frank L. Ferschweiler
  • Patent number: 11083080
    Abstract: Methods and devices that identify a silkscreen data file associated with a physical printed circuit board and use an image of the physical printed circuit board to display a virtual silkscreen over the image of the physical printed circuit board.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 3, 2021
    Assignee: ARRIS Enterprises LLC
    Inventors: Humberto Corral, Carlos Gonzalez Inda, Oswaldo Enrique Linares Rivas, Luis Lopez Moreno, Julio Cesar Ayala Vera, Sergio Antonio Delon Canseco
  • Patent number: 11061321
    Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: July 13, 2021
    Assignee: Synopsys, Inc.
    Inventor: Thomas Cecil
  • Patent number: 11061318
    Abstract: Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hsiang Lo, Hsu-Ting Huang, Ru-Gun Liu
  • Patent number: 11022894
    Abstract: Several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift, tilt of a Bossung curve of a portion of a design layout used in a patterning process for imaging that portion onto a substrate using a lithographic apparatus. The methods include determining or adjusting one or more characteristics of one or more assist features using the one or more rules based on one or more parameters selected from a group consisting of: one or more characteristics of one or more design features in the portion, one or more characteristics of the patterning process, one or more characteristics of the lithographic apparatus, and/or a combination selected from the foregoing.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 1, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Kurt E. Wampler
  • Patent number: 10997352
    Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 4, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Mehmet Can Yildiz, Wen-Hao Liu, Wing-Kai Chow, Zhuo Li, Derong Liu
  • Patent number: 10978449
    Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Hui Chen, Hao-Chieh Chan, Wei-Chih Chen
  • Patent number: 10915090
    Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Danping Peng, Junjiang Lei, Daniel Beylkin, Kenneth Lik Kin Ho, Sagar Trivedi, Fangbo Xu
  • Patent number: 10908598
    Abstract: Examples described herein provide a method for designing an integrated circuit (IC) for meeting different sets of criteria. In an example, different sets of criteria are identified for an IC design. The IC design is designed to meet the different sets of criteria based on expected manufacturing variation. The IC design is caused to be manufactured as IC products. At least some of the IC products are caused to be tested. The IC products are characterized as meeting respective ones of the different sets of criteria based on testing the at least some of the IC products.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 2, 2021
    Assignee: XILINX, INC.
    Inventor: Praful Jain
  • Patent number: 10896883
    Abstract: Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Rasit O Topaloglu
  • Patent number: 10839048
    Abstract: A method and system is provided that simplifies the key management by allowing personalization data protected for one chip model to be used to provision device with another chip model with different global hardware root keys. The solution minimizes the changes needed to be performed on the device during provisioning and remains secure.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 17, 2020
    Assignee: ARRIS Enterprises LLC
    Inventors: Tat Keung Chan, Alexander Medvinsky
  • Patent number: 10810339
    Abstract: A method of determining dimensional changes of features in a mask involves calculating a spacing to be used between adjacent unit cells, correcting a unit cell surrounded by replicas of the same unit cell at the calculated spacing for optical proximity effects, arraying the proximity corrected unit cell at the calculated spacing, and dividing the array of unit cells into templates. Each template frames a portion of the array of unit cells, and locations of the unit cells in each framed template are shifted relative to locations of the unit cells in other framed templates. Critical dimensions for features in the unit cell are determined within each template, and the critical dimensions determined across the template are used to obtain shift variances of each feature. A dimensional change is determined for a feature based on the shift variance for that feature.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: October 20, 2020
    Assignee: Synopsys, Inc.
    Inventor: David Howard Ziger
  • Patent number: 10795267
    Abstract: A method including: obtaining a resist process dose sensitivity value for a patterning process; applying the resist process dose sensitivity value to a stochastic model providing values of a stochastic variable as a function of resist process dose sensitivity to obtain a value of the stochastic variable; and designing or modifying a parameter of the patterning process based on the stochastic variable value.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 6, 2020
    Assignee: ASML Netherlands B.V.
    Inventor: Steven George Hansen
  • Patent number: 10691030
    Abstract: A focus metrology target includes one or more periodic arrays of features. A measurement of focus performance of a lithographic apparatus is based at least in part on diffraction signals obtained from the focus metrology target. Each periodic array of features includes a repeating arrangement of first zones interleaved with second zones, a feature density being different in the first zones and the second zones. Each first zone includes a repeating arrangement of first features. A minimum dimension of each first feature is close to but not less than a resolution limit of the printing by the lithographic apparatus, so as to comply with a design rule in a given a process environment. A region of high feature density may further include a repeating arrangement of larger features.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 23, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Frank Staals, Eric Jos Anton Brouwer, Carlo Cornelius Maria Luijten, Jean-Pierre Agnes Henricus Marie Vaessen
  • Patent number: 10691029
    Abstract: A method including computing a multi-variable cost function, the multi-variable cost function representing a metric characterizing a degree of matching between a result when measuring a metrology target structure using a substrate measurement recipe and a behavior of a pattern of a functional device, the metric being a function of a plurality of design variables including a parameter of the metrology target structure, and adjusting the design variables and computing the cost function with the adjusted design variables, until a certain termination condition is satisfied.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: June 23, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Ning Gu, Daimian Wang, Jen-Shiang Wang
  • Patent number: 10670973
    Abstract: A method includes obtaining a sub-layout having an area that is a performance limiting spot, adjusting colors of patterns in the area, and determining whether the area is still a performance limiting spot. Another method includes decomposing patterns in a design layout into multiple sub-layouts; determining for at least one area in one of the sub-layouts, the likelihood of that a figure of merit is beyond its allowed range; and if the likelihood is above a threshold, that one sub-layout has a performance limiting spot. Another method includes: obtaining a design layout having a first group of patterns and a second group of patterns, wherein colors of the first group of patterns are not allowed to change and colors of the second group of patterns are allowed to change; and co-optimizing at least the first group of patterns, the second group of patterns and an illumination of a lithographic apparatus.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 2, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Yi Zou, Jing Su, Robert John Socha, Christopher Alan Spence, Duan-Fu Stephen Hsu
  • Patent number: 10657641
    Abstract: An illumination source is optimized by changing the intensity and shape of the illumination source to form an image in the image plane that maximizes the minimum ILS at user selected fragmentation points while forcing the intensity at the fragmentation points to be within a small intensity range. An optimum mask may be determined by changing the magnitude and phase of the diffraction orders to form an image in the image plane that maximizes the minimum ILS at user selected fragmentation points while forcing the intensity at the fragmentation points to be within a small intensity range. Primitive rectangles having a size set to a minimum feature size of a mask maker are assigned to the located minimum and maximum transmission areas ad centered at a desired location. The edges of the primitive rectangle are varied to match optimal diffraction orders O(m,n). The optimal CPL mask OCPL(x,y) is then formed.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: May 19, 2020
    Assignee: ASML Netherlands B.V.
    Inventor: Robert Socha
  • Patent number: 10649440
    Abstract: A method of designing and manufacturing a replica composite object based on an original object. The method identifies the structure and physical properties of an original object. Base materials, bodies, and structural templates, each of which includes associated physical properties, are utilized to generate a 3-dimensional model. The 3-dimensional model is discretized and tested to determine if the selected combination of base materials and bodies have physical properties that substantially equal the physical properties of the original object. If the physical properties do not equate, the 3-dimensional model is optimized by adjusting the combination of base materials, bodies, and structural templates. When the difference between the measured physical properties of the 3-dimensional model and the identified physical properties of the original object is less than a tolerance value, the method instructs an additive manufacturing system to generate a replica composite object based on the original object.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 12, 2020
    Assignee: University of Central Florida Research Foundation, Inc.
    Inventors: Fluvio Lobo Fenoglietto, Jack Stubbs
  • Patent number: 10649345
    Abstract: Methods and apparatuses for estimation of at least one parameter of interest of a feature fabricated on a substrate, the feature having a plurality of structure parameters, the structure parameters including the at least one parameter of interest and one or more nuisance parameters. A receiver receives radiation scattered from one or more measured features on the substrate. A pupil generator generates an unprocessed pupil representation of the received radiation. A matrix multiplier multiplies a transformation matrix with intensities of each of a plurality of pixels of the unprocessed pupil representation to determine a post-processed pupil representation in which effects of the one or more nuisance parameters are mitigated or removed. A parameter estimator estimates the at least one parameter of interest based on the post-processed pupil representation.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 12, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Maxim Pisarenco, Markus Gerardus Martinus Maria Van Kraaij, Sebastianus Adrianus Goorden
  • Patent number: 10599130
    Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wootae Kim, Hyung-Ock Kim, Jaehoon Kim, Naya Ha, Ki-Ok Kim, Eunbyeol Kim, Jung Yun Choi, Sun Ik Heo
  • Patent number: 10573606
    Abstract: Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Rasit O Topaloglu
  • Patent number: 10569469
    Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 25, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Yu Cao, Wenjin Shao, Ronaldus Johannes Gijsbertus Goossens, Jun Ye, James Patrick Koonmen
  • Patent number: 10431422
    Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 1, 2019
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Kazuyuki Hagiwara, Robert C. Pack
  • Patent number: 10418245
    Abstract: A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Jie Lee, Joy Cheng
  • Patent number: 10401737
    Abstract: A technique and method for determining a process dose for a beam lithography process includes accessing a data set that enables associating (i) a plurality of measured dimensions of features exposed by beam lithography with (ii) a plurality of different exposure doses, wherein the features were exposed with the different exposure doses, and with (iii) at least one of a plurality of different densities of the exposed features and a plurality of different nominal dimensions of the exposed features. The method also includes providing a model that is parameterized in at least the following parameters (i) measured feature dimension; (ii) exposure dose; (iii) at least one of feature density and nominal feature dimension; (iv) process dose; and (v) at least one process bias. In a further step, the method includes fitting the model with the data set to determine the process dose and the process bias.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 3, 2019
    Assignee: GenISys GmbH
    Inventors: Ulrich Hofmann, Nezih Uenal
  • Patent number: 10395001
    Abstract: A computer implemented method for decomposing a layout of a portion of an integrated circuit is presented. The layout includes a first multitude of polygons. The method includes constructing, using the computer, a first matrix representative of a first multitude of constraints. Each of the first multitude of constraints is between a different pair of the first multitude of polygons. The method includes solving, using the computer, the first matrix to thereby assign one of a multitude of masks to each different one of the first multitude of polygons, when the computer is invoked to decompose the layout.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 27, 2019
    Assignee: SYNOPSYS, INC.
    Inventor: Hua-Yu Chang
  • Patent number: 10331823
    Abstract: A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: June 25, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Trent Lorne McConaghy, Joel Cooper, Jeffrey Dyck, Megan Marsh
  • Patent number: 10198550
    Abstract: Embodiments of the disclosure provide a method including: identifying a target feature in an integrated circuit (IC) layout not represented in a library, the library including a plurality of sub-resolution assist feature (SRAF) usefulness maps corresponding to a plurality of features and SRAFs in the IC layout; generating a usefulness map for the target feature with an artificial neural network (ANN), the generating being based on the target feature and the plurality of SRAF usefulness maps in the library; adding the target feature and the generated usefulness map to the library; selecting an SRAF insertion site for the target feature based on the generated usefulness map; and inserting an SRAF for the target feature into the IC layout at the selected SRAF insertion site.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Andrey A. Lutich
  • Patent number: 10156796
    Abstract: A method to easily determine parameters of a second process for manufacturing from parameters of a first process is provided. Metrics representative of differences between the first process and the second process are computed from a number of values of the parameters, which can be measured for the first process and the second process on a calibration layout, or which can be determined from pre-existing values for layouts or reference data for the first process and the second process by an interpolation/extrapolation procedure. A set of metrics are selected so that their combination gives a precise representation of the differences between the first process and the second process in all areas of a target design. Advantageously, the metrics are calculated as a product of convolution of the target design and a compound of a kernel function and a deformation function.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: December 18, 2018
    Assignee: ASELTA NANOGRAPHICS
    Inventors: Mohamed Saïb, Patrick Schiavone, Thiago Figueiro
  • Patent number: 10007192
    Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: June 26, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jun Ye, Yu Cao, James Patrick Koonmen
  • Patent number: 10004138
    Abstract: Disclosed are an optical member, a display device including the optical member and a method of fabricating the optical member. The display device includes a light source; a wavelength conversion member into which light generated from the light source is incident; and a display panel into which light is incident from the wavelength conversion member. The wavelength conversion member includes a receiving part having a pipe shape; a matrix in the receiving part; and a plurality of wavelength conversion particles disposed in the matrix to convert a wavelength of the light generated from the light source.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: June 19, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Byung Soo Kim, Keun Sik Lee, Chung Won Seo, Ji Won Jo, Hyuk Jin Hong, Yong In Lee
  • Patent number: 9905552
    Abstract: A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Xuelian Zhu, Harry J. Levinson
  • Patent number: 9892221
    Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Jye-Yen Cheng, Wei-Chan Kung
  • Patent number: 9836564
    Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: December 5, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu
  • Patent number: 9805158
    Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 31, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Hongzhou Liu, Stephan Weber, Wangyang Zhang
  • Patent number: 9766548
    Abstract: The present invention provides an exposure apparatus including a projection optical system configured to project light from a reticle onto a substrate, a processor configured to estimate a variation in imaging characteristic of the projection optical system, based on a model determined in advance, and an adjusting device configured to adjust the imaging characteristic of the projection optical system based on the variation estimated by the processor, wherein the processor is configured, if an error of the imaging characteristic of the projection optical system adjusted by the adjusting device based on the variation which is estimated based on a first number of models, for estimating the variation, determined in advance without the reticle, does not fall within a tolerance, to generate a second number of models for estimating the variation, the second number being larger than the first number.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 19, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Bunsuke Takeshita
  • Patent number: 9735029
    Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Albert M. Chu, Lawrence A. Clevenger, Ximeng Guan, Myung-Hee Na
  • Patent number: 9672312
    Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guido Ueberreiter, Paul Ackmann, Guoxiang Ning, Jui-Hsuan Feng, Chin Teong Lim
  • Patent number: 9639647
    Abstract: A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: May 2, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Min Fu, Wan-Yu Lo, Chin-Chou Liu, Huan Chi Tseng
  • Patent number: 9529268
    Abstract: Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Chien-Fu Lee, Hoi-Tou Ng
  • Patent number: 9507902
    Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: November 29, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, David A. Abercrombie, John W. Stedman