Abstract: Various implementations of the invention provide for the optimization of etch induced pattern transfer across a significant portion of a design. In various implementations, an entire design, that is a “full-chip” may be optimized. With some implementations, the invention may be employed to detect etch hotspots. Further implementations may be employed in either or both a mask data preparation process (“MDP”) or to determine the etch effects of including various patterns in a design.

Abstract: A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.

Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of an assist feature to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of an assist feature to image intensity on a main feature. Neighboring regions of the main feature are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the assist feature is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the main feature and the term ? is the position of the assist.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

Abstract: Changing a via density for viafill vias to improve wafer surface planarity for later photolithography is provided, in one embodiment, by obtaining a circuit design including a plurality of viafill vias having differing via density across the circuit design, each viafill via interconnecting non-functional metal fill shapes in different layers of the circuit design; selecting a region of the circuit design to evaluate using an evaluation window; determining a via density within the evaluation window; and changing a number of viafill vias within the region in the circuit design in response to the via density being different than a threshold via density that is selected such that a coating deposited over the plurality of vias presents a substantially planar surface.

Abstract: A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.

Abstract: A method, system, and related computer program products for computer simulation of a photolithographic process is described. In one embodiment, a method for designing an integrated circuit is provided. The geometrical design intent and process condition values are received for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit. The photolithographic process is simulated at the process condition values using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results.

Abstract: In positioning assist features on a photomask pattern to improve the image quality of the main features, the method includes deriving an h-function in a first process which represents a contribution of an assist feature with respect to image intensity at a main feature. In a continuation of the method, the position of the assist features are determined in a second process using the h-function derived in the first step. The assist features are then formed on the mask at the positions indicated. Also included is a computer readable medium having instructions for performing the h-function calculations, and the mask apparatus itself with both main and assist features positioned according to the h-function.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with a corresponding modified cell of the modified library to obtain a modified integrated circuit device layout. The modified library includes modified cells corresponding to cells in the library and candidate areas of each modified cell indicating portions of the cell for further processing. At least some of the modified cells have been modified to at least partially compensate for a manufacturing effect.

Abstract: An embodiment provides systems and techniques for determining a process model. During operation, the system may receive a first optical model which models a first optical system of a photolithography process. Next, the system may use the first optical model to determine a second optical model that models a second latent image that is formed by the first optical system at a second distance. The system may also use the first optical model to determine a third optical model that models a third latent image that is formed by the first optical system at a third distance. Next, the system may receive process data which is obtained by subjecting a test layout to the photolithography process. The system may then determine a process model using the first optical model, the second optical model, the third optical model, the test layout, and the process data.

Abstract: A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.

Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

Abstract: Implementations are presented herein that relate to a standard cell including a measuring structure for controlling process parameters during manufacture of an integrated circuit. A standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit, wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit, wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell, wherein the measuring structure includes at least one feature in at least one of the plurality of material layers and the plurality of mask layers, wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

Abstract: Embodiments of the invention relate to correcting errors in scanning electron measurements during measuring structural dimensions of an integrated circuit for optical proximity correction by extracting feature edges of a test pattern within an image, calculating at least one scaling error of the image by comparing the extracted feature edges of assist structures with a layout pattern, modifying feature edges of test structures within the test pattern by incorporating the at least one scaling error so as to at least partially compensate the scaling errors, and verifying a model for optical proximity corrections and/or model input data by using the modified feature edges of the test structures.

Abstract: A semiconductor integrated circuit device and a fabrication method thereof are disclosed, for effective suppression of a temperature increase therein that is caused by heat generation of a semiconductor element. The semiconductor integrated circuit device includes a semiconductor element, a multi-layer wiring structure and a heat conduction part. The semiconductor element is formed on a support substrate. The multi-layer wiring structure is formed in an insulation film on the support substrate and includes at least one connection hole and at least one metal wiring layer. The heat conduction part is formed of the same conductive materials as the connection hole and the metal wiring layer and extends toward an upper layer side along a path different from a wiring path including a connection hole and a metal wiring for signal transmission.

Abstract: Some embodiments include methods in which a mathematical representation of a photomask construction is defined, with such representation comprising a plurality of pillars that individually contain a plurality of distinct layers. Each of the layers has two or more characteristic parameters which are optimized through an optimization loop. Subsequently, specifications obtained from the optimization loop are utilized to form actual layers over an actual reticle base. Some embodiments include photomask constructions in which a radiation-patterning topography is across a reticle base, with such topography including multiple pillars that individually contain at least seven distinct layers.

Abstract: The present disclosure relates to fracturing of polygon data, with one application being microlithography. In particular, it relates to preserving data regarding edges and/or vertices of the original polygons as the polygons are triangulated and even if the results of triangulation are further fractured.

Abstract: A method for manufacturing a photomask based on design data includes the steps of forming a figure element group including a figure element in a layout pattern on the photomask and a figure element affecting the figure element due to the optical proximity effect, adding identical identification data to a data group indicating an identical figure element group, estimating an influence of the optical proximity effect on the figure element group, generating correction data indicating a corrected figure element in which the influence of the optical proximity effect is compensated for at the time of exposure, creating figure data by associating data having the identical identification data with correction data having the identical identification data, and forming a mask pattern on the photomask using figure data. Thus, the computation time for correction of the layout can be reduced, thereby reducing the production time of the photomask.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached.

Abstract: Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var, zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.

Abstract: A method for determining a mask pattern is described. During the method, a first mask pattern that includes a plurality of second regions corresponding to the first regions of the photo-mask is provided. Then, a second mask pattern is determined based on the first mask pattern and differences between a target pattern and an estimate of a wafer pattern that results from the photolithographic process that uses at least a portion of the first mask pattern. Note that the determining includes different treatment for different types of regions in the target pattern, and the second mask pattern and the target pattern include pixilated images.

Abstract: According to various embodiments of the invention systems and methods for multiple pattern lithography, wherein a target layout pattern that is not capable of being printed in one lithography step is decomposed into multiple patterns that are printable in one lithography operation and, when appropriate, a continuous junction is utilized for where patterns overlap. In a further embodiment, where a continuous junction is not utilized, a splice is utilized at overlap locations. In yet another embodiment, where splices are utilized for overlap locations, identifying where critical nets are located in the target layout pattern, determining how close a component of the critical net is to a splice, and changing the target layout pattern as to avoid the condition of a component of the critical net being in proximity to a splice. In another embodiment of the invention, where splices are utilized at overlap locations, placing a landing pad of contacts or vias at the same location as the splice.

Abstract: A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.

Abstract: Roughly described, method and apparatus for laying out an integrated circuit, in which a subject interconnect has predetermined values for a plurality of variables affecting propagation delay of the subject interconnect. The value of an adjustment one of the variables is adjusted to minimize exposure of the propagation delay of the interconnect to process variations causing variations in the value of a subject fabrication variable, and a revised layout is developed in dependence upon the adjusted value for the adjustment variable. In an embodiment, the adjustment is made in dependence upon a pre-calculated “interconnect optimization database” indicating combinations of values for the plurality of variables which have been pre-determined to minimize exposure of interconnect propagation delay to process variations affecting the subject variable.

Abstract: An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield acceptable results. This category of rules provides more degrees of freedom in actual application so that the rule-based OPC tool can intelligently select the proper valid rule that minimizes the OPC complexity or meets other objectives.

Abstract: A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Abstract: In accordance with the invention, there is provided a system and method for checking a mask layout including sub-resolution assist features (SRAFs). A checking program divides each edge of each main feature into sections, forms a set of segments by searching perpendicularly over a distance to determine if any portion of a feature is located within the distance. Segments are then flagged based on whether a feature located within proximity to that segment. A classification program may then classify each of the main features based on the segment data.

Abstract: In accordance with the invention, there is a method of designing a lithography mask. The method can comprise generating initial phase photomask data and initial trim photomask data from a first set of data from a first drawn layer and/or layout and a second set of data from a second drawn layer, combining the initial phase photomask data with the first set of data to form a combined layer, inspecting for gaps in the combined layer, and processing the gaps in the combined layer.

Abstract: For determining an optimized wafer layout, at least two wafer layouts are specified for a given wafer, each wafer layout defining the location of a plurality of die with regard to the wafer. An optimization parameter value of at least one optimization parameter is determined for each of the at least two wafer layouts. The at least one optimization parameter includes at least one of a number of exposure fields necessary for exposing the respective wafer layout and a number of die of the wafer layout. The optimized wafer layout is selected out of the at least two wafer layouts depending on the optimization parameter values.

Abstract: Provided are a method of fabricating a semiconductor and an apparatus using the method, and more particularly, a method of effectively arranging assist features on the mask and an apparatus using the method. The method of arranging mask patterns includes separately calculating contributions of an assist feature to image intensity at an optimal focus and at a defocus position and placing the assist feature at a position where the contribution of the assist feature to the image intensity is greater at the defocus position than at the optimal focus position.

Abstract: A method of precisely inspecting the entire surface of a mask at a high speed in consideration of optical effects of the mask. The method includes designing a target mask layout for a pattern to be formed on a wafer, and extracting an effective mask layout using an inspection image measured from the target mask layout using an aerial image inspection apparatus as a mask inspection apparatus. The effective mask layout is input to a wafer simulation tool for calculating a wafer image to be formed on the wafer. Optical effects of the mask are detected by comparing the target mask layout with the effective mask layout.

Abstract: Sub-resolution assist features (SRAFs) are placed in a template form and in series adjacent to main features in a layout design. After each SRAF template is placed, a clean-up process is conducted according to clean-up rules if necessary. Both SRAF templates and clean-up rules may be derived by using a model-based method or an optimization approach. Methods according to various embodiments of the invention may be used to place SRAFs near some two-dimensional main features such as contact features.