Abstract: A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell.

Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.

Abstract: A method for processing optical proximity correction includes preparing a chemical mechanical polishing (CMP) map; extracting calibration data depending on a focus degree with the CMP map; and correcting optical proximity with the calibration data.

Abstract: Aspects of the present disclosure provide a method and a system for providing a selection of golden tools for better defect density and product yield. A golden tool selection and dispatching system is provided to integrate different components for robust golden tool selection and dispatching. The golden tool selection system selects a set of golden tools based on performance of a set of manufacturing tools and provides a fully automated operational environment to produce a product using the set of golden tools.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.

Abstract: Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement data is collected from a specific manufacturing environment and sorted by channel lengths. Then, an optimizer is used to generate customized modeling parameters based on the measurement data. The optimization processes is a multi-step process. First, a first set of modeling parameters is generated based on measurement data associated with a long channel length. Second, a second set of modeling parameters is generated based on the first set and on measurement data associated with a short channel length. Finally, the customized modeling parameters are generated based on both the first set and the second set. The customized modeling parameters are used to generate a customized compact device model representative of the specific manufacturing environment.

Abstract: An embodiment of the invention provides a pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters.

Abstract: During a method for generating a third mask pattern to be used on a photo-mask in a photolithographic process, first features are added to a first mask pattern to produce a second mask pattern. A majority of the first features may have a size characteristic larger than a pre-determined value, and that the first features are topologically disconnected from second features in the first mask pattern that overlap third features in a target pattern. Moreover, the first features may be added at positions which are determined based on the gradient of a first cost function depending, at least in part, on the first mask pattern and the target pattern. Then, the third mask pattern may be generated based on the second mask pattern, where the photo-mask corresponds to the third mask pattern.

Abstract: A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may be accomplished by modeling a substrate current component in a third region, in which an inconsistency may occur when a substrate current in a high voltage device is calculated, for example using BSIM3-based modeling. According to embodiments, a substrate current for a third region may be modeled by an expression with a ternary operator, and the modeled substrate current may be added to a substrate current obtained through BSIM3-based modeling.

Abstract: The manufacturability of a lithographic mask employed in fabricating instances of a semiconductor device is determined. Target edge pairs are selected from mask layout data of the lithographic mask, for determining a manufacturing penalty in making the lithographic mask. The mask layout data includes polygons, where each polygon has a number of edges. Each target edge pair is defined by two of the edges of one or more of the polygons. The manufacturability of the lithographic mask, including the manufacturing penalty in making the lithographic mask, is determined. Determining the manufacturing penalty is based on the target edge pairs as selected. Determining the manufacturability of the lithographic mask uses continuous derivatives characterizing the manufacturability of the lithographic mask on a continuous scale. The manufacturability of the lithographic mask is output. The manufacturability of the lithographic mask is dependent on the manufacturing penalty in making the lithographic mask.

Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Abstract: A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based on one or more rules, wherein the metal fill data represents a consolidation of actual metal fill. A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record, the metal fill data representing a virtual metal fill having a configuration that is different from a configuration of actual metal fill.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: The invention can provide a method of processing a substrate using multi-pitch scatterometry targets (M-PSTs) for de-convolving lithographic process parameters during Single-Patterning (S-P), Double-Patterning (D-P) procedures, and Double-Exposure (D-E) procedures used to control transistor structures. The M-PSTs) can have critical dimension (CD) and sidewall angle (SWA) sensitivity to exposure focus variations, exposure dose variations, and post exposure bake (PEB) temperature variations. In addition, the variation can be de-convolved so that the individual measurement process variable contributor can be identified.

Abstract: A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method includes preparing a linewidth map of at least one device of the plurality of devices, performing a topography-aware analysis of the at least one device based on the linewidth map, and designing the optimized specification of the IC based on the topography-aware analysis. In another embodiment, a method for estimating a leakage power of at least one device in an IC is provided. The method includes determining a defocus and a pitch value, determining a linewidth value based on the defocus and pitch value, and estimating the leakage current and/or leakage power based on the linewidth value.

Abstract: Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.

Abstract: A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed.

Abstract: Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.

Abstract: Provided is a method to design an integrated circuit. The method reduces a time delay between introduction of a new lithography process and a start of production. A first semiconductor mask is designed at a first process feature size. The first process feature size can be based on an anticipated process feature size of the new lithography process. A second semiconductor mask is created by enlarging the first semiconductor mask to a second process feature size for which production is available. Thus, the second process feature size is larger than the first process feature size. An integrated circuit (IC) is fabricated with the second semiconductor mask. After the new semiconductor process has been developed and is available for production, another IC is fabricated with the first semiconductor mask.

Abstract: Some embodiments provide techniques and systems to identify locations in a target mask layout for placing assist features. During operation, an embodiment can determine a spatial sampling frequency to sample the target mask layout, wherein sampling the target mask layout at the spatial sampling frequency prevents spatial aliasing in a gradient of a cost function which is used for computing an inverse mask field. Next, the system can generate a grayscale image by sampling the target mask layout at the spatial sampling frequency. The system can then compute the inverse mask field by iteratively modifying the grayscale image. The system can use the gradient of the cost function to guide the iterative modification process. Next, the system can filter the inverse mask field using a morphological operator, and use the filtered inverse mask field to identify assist feature locations in the target mask layout.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: A method of designing a lithographic mask for use in lithographic processing of a substrate is disclosed. The lithographic processing comprises irradiating mask features of a lithographic mask using a predetermined irradiation configuration. In one aspect, the method comprises obtaining an initial design for the lithographic mask comprising a plurality of initial design features having an initial position. The method further comprises applying at least one shift to at least one initial design feature and deriving there from an altered design so as to compensate for shadowing effects when irradiating the substrate using a lithographic mask corresponding to the altered design in the predetermined irradiation configuration. Also disclosed herein are a corresponding design, a method of setting up lithographic processing, a system for designing a lithographic mask, a lithographic mask, and a method of manufacturing it.

Abstract: A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist.

Abstract: An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield.

Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Abstract: A method of fabricating an organic thin film transistor is provided. The method includes forming a source, a drain and a gate on a substrate and forming a dielectric layer to isolate the gate from the source and isolate the gate from the drain. An organic active material layer is formed on the substrate to fill a channel region between the source and the drain and cover the source and the drain. A barrier material layer is formed on the organic active material layer. Thereafter, the barrier material layer and the organic active material layer are patterned to form a barrier layer and an organic active layer and expose the source and the drain.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.

Abstract: First and second evaluation substrates are prepared, a direction perpendicular to a surface of the first evaluation substrate being defined by first indices, and the direction defined by the first indices being inclined from a normal direction of a surface of the second evaluation substrate. Ion implantation is performed for the first evaluation substrate in a vertical direction. Ion implantation is performed for the second evaluation substrate by using an ion beam parallel to the direction defined by the first indices. Impurity concentration distributions in a depth direction of the first and second evaluation substrates are measured. A first impurity concentration distribution on an extension line of an ion beam and a second impurity concentration distribution in a direction perpendicular to the extension line are predicted from the measured impurity concentration distributions of the first and second evaluation substrates.

Abstract: A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature.

Abstract: The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical.

Abstract: A method of generating complementary masks for use in a dark field double dipole imaging process. The method includes the steps of identifying a target pattern having a plurality of features, including horizontal and vertical features; generating a horizontal mask based on the target pattern, where the horizontal mask includes low contrast vertical features. The generation of the horizontal mask includes the steps of optimizing the bias of the low contrast vertical features contained in the horizontal mask; and applying assist features to the horizontal mask. The method further includes generating a vertical mask based on the target pattern, where the vertical mask contains low contrast horizontal features. The generation of the vertical mask includes the steps of optimizing the bias of low contrast horizontal features contained in the vertical mask; and applying assist features to the vertical mask.

Abstract: The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database, the drawn pattern data describing device circuit features and dummy features. The dummy features have first target patterns. Mask pattern data is generated for the dummy features, wherein one or more of the dummy features have second target patterns that are different from the first target patterns. The mask pattern data is corrected for proximity effects.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.

Abstract: A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

Abstract: A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size.

Abstract: In a multi-project-chip semiconductor device, semiconductor elements fabricated on a wafer have a layout that corresponds to an exposure order of a pattern of the semiconductor elements and that is based on information indicating manufacture conditions and the number of shots and are arranged such that the semiconductor elements having the same manufacture condition are adjacent to each other in ascending or descending order of the number of shots.

Abstract: A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

Abstract: A method for creating a pattern on a photomask includes steps of recognizing a space between main patterns by using pattern data which indicate the main patterns to be adjacently transferred onto a wafer, determining a 1st rule about arrangement of an assist pattern on the photomask, the assist pattern being adjacent to the main patterns and not being transferred onto the wafer, estimating a depth of focus in the presence of the assist pattern among the main patterns, determining a 2nd rule about arrangement of the assist pattern on the photomask to improve the depth of focus in the presence of the 1st assist pattern among the main patterns in a group having one or more number of appearance times of the space between main patterns, and correcting the assist pattern on the photomask using the assist pattern data on the basis of the 2nd rule.

Abstract: A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.

Abstract: Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Abstract: A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system.

Abstract: A method for forming a semiconductor device includes performing a first optimization of a first edge location of a feature fragment, wherein the first optimization has a first speed per fragment, and performing a second optimization of a second edge location of the feature fragment, wherein the second optimization has a second speed per fragment that is slower than the first speed per fragment. Next, a result of the second optimization is used to form a reticle pattern; and a layer on a semiconductor wafer is patterned using the reticle pattern.

Abstract: Disclosed are an improved method, system, and computer program product for a method or system with concurrent models to more accurately determine and represent the three-dimensional design features of electronic designs. Some embodiments disclose a method or a system for determining the design feature characteristics based upon their respective three-dimensional profiles. Some other embodiments further determine whether the design objectives or constraints are met or may be relaxed based upon the design feature characteristics in order to complete the design. Other embodiments store the profile or geometric characteristics, or information derived therefrom, in a database associated with the design to reduce the need for potentially expensive computations. The method or system may modify the designs or the processes to reflect whether the design objectives or constraints are met or relaxed.

Abstract: An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Abstract: A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

Abstract: Various implementations of the invention provide for the optimization of etch induced pattern transfer across a significant portion of a design. In various implementations, an entire design, that is a “full-chip” may be optimized. With some implementations, the invention may be employed to detect etch hotspots. Further implementations may be employed in either or both a mask data preparation process (“MDP”) or to determine the etch effects of including various patterns in a design.