Abstract: A mask layout is received. An interaction-free mask model is applied to the mask layout. An edge interaction model is applied to the mask layout. The edge interaction model describes an influence due to a plurality of combinations of two or more edges interacting with one another. A thin mask model is applied to the mask layout. A near field is determined based on the applying of the interaction-free mask model, the applying of the edge interaction model, and the applying of the thin mask model.

Abstract: Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

Abstract: A routing process applied to design integrated circuits uses keep-through regions. Keep-through regions specify areas which metal shapes may overlap but where metal shapes may not have line ends. The keep-through regions are generated based on end-of-line rules applicable to routing of the design. These keep-through regions are then used in determining the layout of interconnects for the design.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A boundary condition between blocks is formulated by the Barycenter compact model. Boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

Abstract: The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.

Abstract: According to one embodiment, a method of displaying model includes: sampling a pattern to acquire an attention point; calculating a spatial or planar distribution that indicates any one of a design density, a lithography target density, a mask transmittance, or an optical image intensity at N points (N being an integer equal to or greater than 1) on the pattern including the attention point; calculating a threshold for the pattern; estimating, based on the distribution and the threshold, N elements respectively corresponding to the N points as a model; and displaying the estimated model.

Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

Abstract: A noise map is used for defect detection. One or more measurements of intensities at one or more pixels are received and an intensity statistic is determined for each measurement. The intensity statistics are grouped into at least one region and stored with at least one alignment target. A wafer can be inspected with a wafer inspection tool using the noise map. The noise map can be used as a segmentation mask to suppress noise.

Abstract: A metrology target may include a first rotationally symmetric working zone with one or more instances of a first pattern and a second rotationally-symmetric working zone with one or more instances of a second pattern, where at least one of the first pattern or the second pattern is a Moiré pattern formed from a first grating structure with a first pitch along a measurement direction on a first sample layer and a second grating structure with a second pitch different than the first pitch along the measurement direction on a second sample layer. Centers of rotational symmetry of the first and second working zones may overlap by design when an overlay error between the first sample layer and the second layer is zero. A difference between the centers of rotational symmetry of the first and second working zones may indicate an overlay error between the first and second sample layers.

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Abstract: Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.

Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: In one embodiment, a device obtains certificate information for a plurality of network addresses. The device constructs, based on the certificate information, a bipartite graph that maps nodes representing common names from the certificate information to nodes representing autonomous systems. The device determines edge counts from the bipartite graph for the nodes representing the autonomous systems. The device identifies, based on the edge counts, a particular one of the common names as botnet-related by comparing edge counts for the autonomous systems associated with that particular common name to edge counts for the autonomous systems associated with one or more of the other common names.

Abstract: A system may include a model calibration engine configured to determine a candidate lithography model set from which to calibrate a lithography model according to multiple objectives, including by initializing a population of parent candidate models, generating child candidate models, merging the parent and child candidate models into a merged population, classifying the candidate models of the merged population into tiers of non-dominated fronts according to respective objective functions for the multiple objectives, determining a subset of the merged population based on the classified tiers, and identifying, as the candidate lithography model set, a Pareto-optimal front of the subset of the merged population determined based on the classified tiers. The system may also include a model selection engine configured to set a given candidate lithography model in the candidate lithography model set as a calibrated lithography model for simulating a lithographic process.

Abstract: A system for reducing printable defects on a pattern mask is disclosed. The system includes a controller configured to be communicatively coupled to a characterization sub-system, the controller including one or more processors configured to execute program instructions causing the one or more processors to: direct the characterization sub-system to perform inspection of a mask blank; generate a cost function based on a first characteristic and a second characteristic, the first characteristic comprising areas of defect regions exposed by mask patterns, the second characteristic comprising pattern complexity of a design pattern; determine one or more values indicative of a minimum of the cost function via a non-linear optimization procedure; and generate one or more control signals to adjust rotation and translation of the mask blank relative to the design pattern based on the determined one or more values indicative of the minimum of the cost function.

Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: There is provided a system and method of examination of a semiconductor specimen using an examination recipe. The method includes obtaining a registered image pair, for each design-based structural element associated with a given layer, calculating an edge attribute, using a trained classifier to determine a class of the design-based structural element, and generating a layer score usable to determine validity of the registered image pair. There is also provided a system and method of generating the examination recipe usable for examination of a semiconductor specimen.

Abstract: In a method of manufacturing a photomask, a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate is designed. A layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region is designed. The monitoring mask pattern includes a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer. A first optical proximity correction (OPC) is performed on the mask-CDU detection pattern. A second optical proximity correction is performed on the wafer-CDU detection pattern. A photomask having the circuit mask pattern and the monitoring mask pattern is formed.

Abstract: A mask process development having a consistent mask targeting is described. A method includes receiving an integrated circuit (IC) design. A test mask is generated that converts the IC design into one or more physical layouts. A set of one or more sub-resolution assist features (SRAFs) is inserted into the test mask. The set of one or more SRAFs is inserted into one or more other masks, which are derived from the test mask for mask targeting, such that the test mask and the one or more other masks include a same set of the one or more SRAFs.

Abstract: An integrated platform is provided that enables the various steps of development operations from design to sales, the virtualization, the visualization and the interpretation of a device so it may be fully created (designed), viewed, manipulated, packaged, simulated, tested, published and marketed right from within the platform. The resulting virtual device (VD) may be a multi-layered, -dimensional, -angular, -disciplinary, -documentarian, -service, manipulated and used in multiple ways. The provided VD may include visual representations of the VD via a traditional display device in a non-immersive environment and/or within an immersive environment via new virtual-reality (VR) devices. For instance, a user may create, manipulate, in real-time, layered multi-dimensional views of a VD in a virtual-reality, augmented-reality (AR), augmented virtual-reality (AVR), and/or mixed-reality (MR) environments.

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Abstract: The disclosed computer-implemented method may include a display calibration apparatus. The display calibration apparatus may include a lens and an actively-cooled electromagnetic radiation detector configured to detect electromagnetic radiation emitted from various pixels of an electronic display panel under test. The electromagnetic radiation may travel through the lens prior to reaching the detector. The display calibration apparatus may also include a special-purpose computing device configured to: analyze the detected electromagnetic radiation from the pixels of the electronic display panel and generate calibration data for the electronic display panel using a specified calibration algorithm. As such, the electronic display panel may operate using the generated calibration data. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method, including: obtaining a set of conditions for a resist development model for simulating a resist development process of a resist layer; and performing, by a hardware computer system, a computer simulation of the resist development process using the set of conditions and the resist development model to obtain a characteristic of the development of the resist layer, wherein the computer simulation separately simulates different certain different physical and chemical processes and characteristics of the resist development process.

Abstract: Systems, methods, devices, and non-transitory media of the various embodiments enable converting massive mesh datasets that may carry a single material to a hierarchical format. Various embodiments may provide processing efficiency and scalability in creating hierarchical format representations of massive mesh datasets and/or in rendering massive mesh datasets.

Abstract: There are provided a system and method of defect detection on a specimen, the method comprising: performing partitioning for each of one or more portions of a first die; receiving one or more noise maps indicative of noise distribution on second images captured for one or more portions of a second die; performing segmentation for each noise map in runtime, the segmentation for a given noise map including: calculating a score for each region, the given noise map aligned with the regions and each region is associated with noise data aligned therein, the score for a given region calculated at least based on the noise data associated therewith; and associating each region with one segmentation label of a predefined set of segmentation labels indicative of noise levels based on the score, thereby obtaining a set of segments each corresponding to one or more regions associated with the same segmentation label.

Abstract: Examples herein describe techniques for optimizing a hardware design for an integrated circuit. Instead of trying multiple optimization strategies each time design code is synthesized, the embodiments herein describe identifying the optimal or best optimization strategy for a particular combinational module in the design code only one time. Then, each time the design code is synthesized in the future, a synthesis tool recognizes the combinational module and selects the best optimization strategy. To do so, the synthesis tool generates a signature using the circuit structure represented by a netlist. The synthesis tool traverses the netlist and assigns unique integers to the primary inputs, the combination instances, and the primary outputs. These integers can then be fed into a signature generator which outputs a signature for the combinational module.

Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.

Abstract: A display panel comprises a first substrate and a shading layer. The first substrate comprises a plurality of pixel zones arranging in an array form. Each of the pixel zones comprises a first color LED and a second color LED. The first color LED comprise a first light-emitting surface in a display direction. The second color LED comprise a second light-emitting surface in the display direction. An area of the first light-emitting surface is larger than an area of the second light-emitting surface. The shading layer is disposed in the plurality of pixel zones, and the shading layer overlaps some of the first light-emitting surfaces at the display direction.

Abstract: A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment.

Abstract: A wiring configuration tool may be configured to determine a new wiring configuration for a replacement HVAC controller based, at least in part, on the existing wiring configuration for a current HVAC controller and, for example, the make and model of the replacement HVAC controller. The wiring configuration tool may be hosted by a server that provides a user interface for interacting with the user. The user may access the wiring configuration tool via a web services interface, a smart phone application or in any other suitable manner.

Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: A search apparatus receives an input target value, which indicates a condition to be set in a semiconductor processing apparatus or a result obtained by processing the semiconductor using the processing apparatus, a reference value of the condition inside a search area, and the result, wherein the reference value is indicated by the target value. A prediction model indicating a relation between the condition and the result based on a setting value of the condition inside the search area is generated and, a measured value of the result is obtained. A prediction value is acquired by assigning the target value to the prediction model. The prediction value is set to the reference value when it is determined that the prediction value is closer to the target value, and a prediction value satisfying an achievement condition is set when the prediction value satisfies the achievement condition of the target value.

Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium which may be used to produce a photomask for manufacturing an integrated circuit.

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.

Abstract: A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.

Abstract: An approach for shifting a cut associated with a lineend of an interconnect in a manufacturing system. The approach selects one or more polygons associated with the lineend and determines whether a first cut is spanning the one or more polygons. The approach responds to the first cut does span, determines a presence of a first via on a first interconnect and determines a first distance of the first via to the first cut. The approach determines whether the first distance is greater than a first threshold and responds to the first distance is greater and determines whether the first distance is greater and determines a second distance of the first cut to a second cut. The approach determines whether the second distance is greater than a second threshold and responds to the second distance is greater and generates a shift associated with the first cut and outputs the shift.

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Abstract: A layout method is disclosed that includes: placing function cells in a layout, corresponding to at least one design file, of an integrated circuit; and inserting at least one fill cell that is configured without cut pattern to fill at least one empty region between the function cells each comprising at least one cut pattern on at least one edge abutting the at least one empty region.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.

Abstract: The invention is a method for controlling the activity of two light radiation sources (2, 3) belonging to a stereolithography machine (1) and suited to act at the level of a portion (104) of a superimposition area (101) defined on the work surface (100) of the stereolithography machine (1) for the production of a three-dimensional object (200) through stereolithography. For each one of the lines (210) with generic length L that define each layer (201) of the three-dimensional object (200) within the portion (104), the method provides for activating: a first light radiation source (2) for a first section (211) of the line (210) having length X; a second light radiation source (3) for the remaining second section (212) of the line (210) having length Y, wherein the value X of the first section (211) is selected within the interval 0<=X<=L and wherein Y is calculated as equal to L?X.