Layout Generation (polygon, Pattern Feature) Patents (Class 716/55)
  • Patent number: 10311165
    Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: June 4, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Junjiang Lei, Le Hong, Yuansheng Ma
  • Patent number: 10310468
    Abstract: The invention is a method for controlling the activity of two light radiation sources (2, 3) belonging to a stereolithography machine (1) and suited to act at the level of a portion (104) of a superimposition area (101) defined on the work surface (100) of the stereolithography machine (1) for the production of a three-dimensional object (200) through stereolithography. For each one of the lines (210) with generic length L that define each layer (201) of the three-dimensional object (200) within the portion (104), the method provides for activating: a first light radiation source (2) for a first section (211) of the line (210) having length X; a second light radiation source (3) for the remaining second section (212) of the line (210) having length Y, wherein the value X of the first section (211) is selected within the interval 0<=X<=L and wherein Y is calculated as equal to L?X.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: June 4, 2019
    Assignee: DWS S.R.L.
    Inventor: Roberto Fortunato
  • Patent number: 10303839
    Abstract: Methods and systems for determining electrically relevant placement of metrology targets using design analysis are disclosed. The method may include: identifying at least one critical design element of an integrated circuit based on a design of the integrated circuit; determining whether the design of the integrated circuit allows for an insertion of a metrology target in a vicinity of the at least one critical design element; and modifying the design of the integrated circuit by inserting a metrology target into the vicinity of the at least one critical design element when the design of the integrated circuit allows for the insertion of the metrology target.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 28, 2019
    Assignee: KLA-Tencor Corporation
    Inventor: Sagar A. Kekare
  • Patent number: 10296681
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 21, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Guangqing Chen, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Patent number: 10295988
    Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Synopsys, Inc.
    Inventor: Ankush Bharati Oberai
  • Patent number: 10290087
    Abstract: There are provided system and method of generating an examination recipe usable for examining a specimen, the method comprising: capturing images from dies and obtaining noise map indicative of noise distribution on the images; receiving design data representative of a plurality of design groups each having the same design pattern; calculating a group score for each given design group, the group score calculated based on the noise data associated with the given design group and a defect budget allocated for area of the given design group; providing segmentation related to the dies, comprising: associating design groups with segmentation labels indicative of different noise levels based on the group score, thereby obtaining a set of die segments each corresponding to one or more design groups associated with the same segmentation label and segmentation configuration data; and generating an examination recipe using the segmentation configuration data.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 14, 2019
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Ariel Shkalim, Moshe Amzaleg, Eyal Neistein, Shlomo Tubul, Mark Geshel, Elad Cohen
  • Patent number: 10283437
    Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: May 7, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Richard T. Schultz, Omid Rowhani, Charles P. Tung
  • Patent number: 10268792
    Abstract: A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. The schematic design tool computes layout structure data based on the temporary layout and provides the layout structure data to a place and route tool within the design tool system that, in turn, generates a layout based on the layout structure data The design tool system then generates mask layer data based upon the layout that is configured to generate masks for construction of an integrated circuit corresponding to the analog circuit schematic.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: April 23, 2019
    Assignee: NXP USA, INC.
    Inventor: Julia Perez
  • Patent number: 10261412
    Abstract: A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. The method further includes forming a subset of the shapes including the shapes associated with the at least one layout conflict. The method further includes categorizing the shapes of the subset into one of a multitude of topology types, generating stitch candidate solutions for the multitude of topology types, and decomposing the design into a multitude of masks. The subset of the multitude of shapes is formed by generating a first graph representative of the design, decomposing the first graph into at least three colors to form a colored graph; and identifying within the first graph, a second graph including at least one conflict edge.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 16, 2019
    Assignee: Synopsys, Inc.
    Inventors: Soo Han Choi, Srini Arikati, Erdem Cilingir
  • Patent number: 10198543
    Abstract: A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 5, 2019
    Assignee: SYNOPSYS, INC.
    Inventor: Kevin Knapp
  • Patent number: 10162929
    Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Kai Hsu, Yuan-Te Hou, Wen-Hao Chen
  • Patent number: 10151971
    Abstract: A method, of seeding an optical proximity correction (OPC) process, includes: receiving, at an input device of a computer, a subject pre-OPC design-signature for a subject pre-OPC design package; selecting, by the processor and via interaction with an OPC database operatively connected to the computer, one amongst archived post-OPC design packages based on relatedness between the subject pre-OPC design-signature and archived post-OPC design-signatures corresponding to the archived post-OPC design packages, and thereby retrieving the selected archived post-OPC design packages; and generating one or more seeds for the OPC process based on the selected archived post-OPC design package.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yin-Chuan Chen, Chi-Ming Tsai, Shin-Huang Chen
  • Patent number: 10153130
    Abstract: A charged particle beam drawing apparatus has a drawing unit including a charged particle source, a deflector and a stage on which a target object is placed, to perform drawing with a charged particle beam on a plurality of drawing regions on the target object, and a calculator to calculate a drawing progress ratio on the target object using a ratio of a drawn area of the drawing regions to a total area of the drawing regions.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: December 11, 2018
    Assignee: NuFlare Technology, Inc.
    Inventor: Sumito Nakada
  • Patent number: 10089430
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 2, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Patent number: 10019548
    Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 10019547
    Abstract: According to one embodiment, a guide pattern data correcting method is for correcting guide pattern data of a physical guide for formation of a polymer material to be microphase-separated. The physical guide has a plurality of concave portions in the guide pattern data, and at least two concave portions out of the plurality of concave portions are connected to each other. The guide pattern data is subjected to correction by shifting or rotation of at least either of the two connected concave portions.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroki Yonemitsu
  • Patent number: 10008036
    Abstract: In a system for facilitating mesh generation corresponding to a volumetric, prismatic object, generalized polyhedrons representing at least a portion of a layer of the volumetric object are transformed into a set of convex polyhedrons based on, at least in part, the prismatic properties of the volumetric object. The convex polyhedrons corresponding to a layer are decomposed into a set of tetrahedrons by accounting for an intersecting and/or overlapping edge of a polyhedron in an adjacent layer, so that the set of tetrahedrons automatically, i.e., without having to enforce any continuity requirements after tetrahedron generation, forms a mesh of that is continuous with tetrahedrons corresponding to the adjacent layer.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: June 26, 2018
    Assignee: Ansys, Inc.
    Inventor: Ravi Sundaram
  • Patent number: 9971863
    Abstract: A method is disclosed that includes determining whether there is a conflict graph representing that each spacing between any two of at least five adjacent patterns of multiple-patterning patterns of a layout of an integrated circuit (IC) is less than a threshold spacing, and if there is the conflict graph, modifying the multiple-patterning patterns to exclude patterns represented by the conflict graph, for fabrication of the IC.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 15, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Kai Hsu, Yuan-Te Hou, Wen-Hao Chen
  • Patent number: 9971478
    Abstract: A method of displaying a plurality of graphical user interface elements, each graphical user interface element representing a step in a measurement design, setup and/or monitoring process and each graphical user interface element enabling access by the user to further steps in the measurement design, setup and/or monitoring process for the associated step of the graphical user interface element, and displaying an indicator associated with one or more of the plurality of graphical user elements, the indicator indicating that a step in the measurement design, setup and/or monitoring process is not completed and/or that a key performance indicator associated with a step in the measurement design, setup and/or monitoring process has passed a threshold.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 15, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Everhardus Cornelis Mos, Erik Mathijs Maria Crombag, Ajith Ganesan
  • Patent number: 9922212
    Abstract: A MMIC (microwave monolithic integrated circuit) based FET mixer and method for the same is provided. In particular, adjacent transistors, such as FETs (field effect transistors) share terminals reducing physical layout separation and interconnections. A smaller die size is realized with the improved system geometry herein provided.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 20, 2018
    Assignee: VIASAT, INC.
    Inventor: Kenneth V. Buer
  • Patent number: 9899190
    Abstract: A method of manufacturing a substrate is disclosed. The method includes receiving a plurality of pixel elements, wherein each of the pixel elements includes data members; and transferring the data members to a plurality of exposing devices that are configured to conditionally expose the substrate with an incident energy beam when coupled with the data members, wherein different data members of one pixel element are transferred at different system cycles.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Chi Chen
  • Patent number: 9886539
    Abstract: A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-Synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells for the integrated circuit. The method may further include determining, using a cross-probe criterion, an amount of cross-correlation between a first cell and a second cell in the gate-level netlist. The method may further include generating, in response to the amount of cross-correlation exceeding a correlation threshold, a cell group including the first cell and the second cell. The method may further include determining a boundary condition for the cell group. The method may further include generating a floorplan. The first cell and the second cell may be placed in the floorplan according to the boundary condition.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: February 6, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mani Viswanath, Thomas Mitchell
  • Patent number: 9852260
    Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Kafai Lai, Chi-Chun Liu, Ananthan Raghunathan, Hsinyu Tsai
  • Patent number: 9852249
    Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
  • Patent number: 9847108
    Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 19, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Muneaki Matsushige, Atsunori Hirobe, Kazutaka Kikuchi, Tetsuo Fukushi
  • Patent number: 9798847
    Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha
  • Patent number: 9754064
    Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: September 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chuan-Fang Su, Kun-Zhi Chung, Yuan-Hsiang Lung
  • Patent number: 9684753
    Abstract: In one aspect, a CAD-based method for designing a lithographic mask for nanowire-based devices is provided which includes the steps of: create a design for the mask from existing (e.g., FINFET or planar CMOS) design data which includes, for each of the devices, one or more nanowire mask shapes (FINFET design data) or continuous shapes (planar CMOS design data); for FINFET design data, merging the nanowire mask shapes into continuous shapes; expanding the continuous shapes to join all of the continuous shapes in the design together forming a single polygon shape; removing the continuous shapes from the single polygon shape resulting in landing pad shapes for anchoring the nanowire mask shapes; for CMOS design data, dividing the continuous active shapes into one or more nanowire mask shapes; and merging the landing pad shapes with the nanowire mask shapes to form the lithographic mask.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: June 20, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 9659141
    Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Cheng-I Huang, Chin-Chang Hsu, Hung Lung Lin
  • Patent number: 9659128
    Abstract: Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chang Huang, Ying Ying Wang, Shellin Liu, Kuan-Chi Chen
  • Patent number: 9588415
    Abstract: An exposure system includes a data processing part that forms an exposure layout and an exposure part that irradiates an electron beam at a photoresist layer according to the exposure layout. The data processing part generates a control parameter for driving the exposure part without a pattern position error and a beam drift error and to prevent a discrepancy between the exposure layout and a mask layout to be formed in the photoresist layer. A controlling part controls the exposure part according to the control parameter.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukjong Bae, Jin Choi, Sunghoon Park
  • Patent number: 9583305
    Abstract: An exposure method may include: radiating a charged particle beam in an exposure system comprising a beam generator, radiating the beam, and main and auxiliary deflectors deflecting the beam to determine a position of a beam shot; determining whether a deflection distance from a first position of a latest radiated beam shot to a second position of a subsequent beam shot is within a first distance in a main field area of an exposure target area, the main field area having a size determined by the main deflector; setting a settling time according to the deflection distance so that a settling time of the subsequent beam shot is set to a constant minimum value, greater than zero, when the deflection distance from the first position to the second position is within the first distance; and deflecting the beam using the main deflector based on the set settling time.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Seok Jung, Shuichi Tamamushi, In-Hwan Noh, In-Kyun Shin, Sang-Hee Lee, Jin Choi
  • Patent number: 9569576
    Abstract: A mask data generating method for generating data of a plurality of masks used in a plurality of exposures in which exposure light is irradiated onto a substrate using a mask, and then exposure light is irradiated onto the substrate using another mask. The method includes the steps of obtaining data for a pattern including a plurality of pattern elements, determining formulation of a disposition limitation condition for the pattern elements, analyzing the distance between the pattern elements, determining formulation of the distance limitation condition, and applying a first variable configured to express a number of pattern divisions and a second variable configured to express a distance related to all pattern elements in a cost function and thereby dividing the pattern.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 14, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tadashi Arai, Yuichi Gyoda
  • Patent number: 9563738
    Abstract: An optical proximity correction (OPC) process is provided. The method comprising receiving a first pattern corresponding to a first structure of a semiconductor structure, and a second pattern corresponding to a second structure of said semiconductor structure. Next, a first OPC process is performed for the first pattern to obtain a revised first pattern, wherein the revised first pattern has a first shift regarding to the first pattern. A second OPC process is performed for the second pattern to obtain a revised second pattern, wherein the second OPC process comprises moving the second pattern according to the first shift.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: February 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hung Chen, Chin-Lung Lin, Kuan-Wen Fang, Po-Ching Su, Hung-Wei Lin, Sheng-Lung Teng, Lun-Wen Yeh
  • Patent number: 9553033
    Abstract: Methods and tools for generating measurement models of complex device structures based on re-useable, parametric models are presented. Metrology systems employing these models are configured to measure structural and material characteristics associated with different semiconductor fabrication processes. The re-useable, parametric sub-structure model is fully defined by a set of independent parameters entered by a user of the model building tool. All other variables associated with the model shape and internal constraints among constituent geometric elements are pre-defined within the model. In some embodiments, one or more re-useable, parametric models are integrated into a measurement model of a complex semiconductor device. In another aspect, a model building tool generates a re-useable, parametric sub-structure model based on input from a user.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: January 24, 2017
    Assignee: KLA-Tencor Corporation
    Inventors: Jonathan Iloreta, Matthew A. Laffin, Leonid Poslavsky, Torsten Kaack, Qiang Zhao, Lie-Quan Lee
  • Patent number: 9541835
    Abstract: According to one embodiment, a guide pattern data correcting method is for correcting guide pattern data of a physical guide for formation of a polymer material to be microphase-separated. The physical guide has a plurality of concave portions in the guide pattern data, and at least two concave portions out of the plurality of concave portions are connected to each other. The guide pattern data is subjected to correction by shifting or rotation of at least either of the two connected concave portions.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: January 10, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Yonemitsu
  • Patent number: 9520482
    Abstract: A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate. The first fin has a first gate region and the second fin has a second gate region. The method also includes forming a metal-gate line over the first and second gate regions. The metal-gate line extends from the first fin to the second fin. The method also includes applying a line-cut to separate the metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming an isolation region within the line cut.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: December 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chin Chang, Chih-Hao Wang, Kai-Chieh Yang, Shih-Ting Hung, Wei-Hao Wu, Gloria Wu, Inez Fu, Chia-Wei Su, Yi-Hsuan Hsiao
  • Patent number: 9514266
    Abstract: A method of determining colorability of a layout includes generating a conflict diagram based on circuit information. The conflict diagram includes a plurality of nodes, each node of the plurality of nodes is connected to at least another node of the plurality of nodes by a link, and each node of the plurality of nodes has a degree equal to a number of links connected to the node. The method includes setting a degree of each anchor node within the conflict diagram to a value of n, where n is equal to a number of mask usable to manufacture the layout. The method further includes excluding, using a processor, nodes having a degree less than n from the conflict diagram. The method further includes performing a color status check on the conflict diagram after the excluding; and determining whether the layout is colorable based on the performed color status check.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Chun Huang, Wen-Ju Yang
  • Patent number: 9508650
    Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: November 29, 2016
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 9502354
    Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: November 22, 2016
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Michio Inoue, Yorio Takada
  • Patent number: 9454631
    Abstract: Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen E. Greco, Vincent J. McGahay, Rasit O. Topaloglu
  • Patent number: 9436787
    Abstract: The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyuh-Fuh Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Shy-Jay Lin, Burn Jeng Lin
  • Patent number: 9436789
    Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9405186
    Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Amr Y. Abdo, Nathalie Casati, Maria Gabrani, James M. Oberschmidt, Ramya Viswanathan, Josef S. Watts
  • Patent number: 9401046
    Abstract: Micropolygon splatting may involve tessellating by subdividing a mesh until triangle edges are shorter than 0.75 pixels. In some cases, rasterizing the primitive may be avoided.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 26, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Möller, Jon N. Hasselgren, Robert M. Toth
  • Patent number: 9395631
    Abstract: Multi-beam pattern generators employing yaw correction when writing upon large substrates, and associated methods are disclosed. A multi-beam pattern generator may include a spatial light modulator (SLM) with independently controllable mirrors to reflect light onto a substrate to write a pattern. The pattern may be written in writing cycles where the substrate is moved to writing cycle zone locations. The light is reflected by the SLM onto the substrate by mirrors of the SLM in active positions to write the pattern upon the substrate. By determining a location and yaw of the substrate with respect to the SLM in each writing cycle, some mirrors of the SLM may be digitally controlled to either inactive positions or the active positions to compensate for the yaw of the substrate. In this manner, the pattern written upon the substrate may be precisely written with compensation for yaw.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: July 19, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Christopher Bencher
  • Patent number: 9349786
    Abstract: An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: May 24, 2016
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Amro M. Elshurafa, Ahmed Gomaa Ahmed Radwan, Ahmed A. Emira, Khaled Nabil Salama
  • Patent number: 9297856
    Abstract: A method and circuits for implementing multiple input signature register (MISR) compression for test time reduction, and a design structure on which the subject circuits reside are provided. The MISR compression circuit includes a first MISR, a second MISR provided with the first MISR, and a compressor to compress MISR data positioned in one of between the first MISR and second MISR and after the second MISR.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Mary P. Kusko, Cédric Lichtenau
  • Patent number: 9291902
    Abstract: The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask or mask set. In particular, it relates to customizing a latent image formed in a patterning sensitive layer over a substrate, merging standard and custom pattern data to form a custom pattern used to produce the customized latent image. A wide variety of substrates can benefit from the technology disclosed.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 22, 2016
    Assignee: Mycronic AB
    Inventors: Lars Ivansen, Anders Osterberg
  • Patent number: 9286434
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Yi Zou, Wei-Long Wang, Azat Latypov, Tamer Coskun