Abstract: Systems, methods, devices, and non-transitory media of the various embodiments enable converting massive mesh datasets that may carry a single material to a hierarchical format. Various embodiments may provide processing efficiency and scalability in creating hierarchical format representations of massive mesh datasets and/or in rendering massive mesh datasets.

Abstract: There are provided a system and method of defect detection on a specimen, the method comprising: performing partitioning for each of one or more portions of a first die; receiving one or more noise maps indicative of noise distribution on second images captured for one or more portions of a second die; performing segmentation for each noise map in runtime, the segmentation for a given noise map including: calculating a score for each region, the given noise map aligned with the regions and each region is associated with noise data aligned therein, the score for a given region calculated at least based on the noise data associated therewith; and associating each region with one segmentation label of a predefined set of segmentation labels indicative of noise levels based on the score, thereby obtaining a set of segments each corresponding to one or more regions associated with the same segmentation label.

Abstract: Examples herein describe techniques for optimizing a hardware design for an integrated circuit. Instead of trying multiple optimization strategies each time design code is synthesized, the embodiments herein describe identifying the optimal or best optimization strategy for a particular combinational module in the design code only one time. Then, each time the design code is synthesized in the future, a synthesis tool recognizes the combinational module and selects the best optimization strategy. To do so, the synthesis tool generates a signature using the circuit structure represented by a netlist. The synthesis tool traverses the netlist and assigns unique integers to the primary inputs, the combination instances, and the primary outputs. These integers can then be fed into a signature generator which outputs a signature for the combinational module.

Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.

Abstract: A display panel comprises a first substrate and a shading layer. The first substrate comprises a plurality of pixel zones arranging in an array form. Each of the pixel zones comprises a first color LED and a second color LED. The first color LED comprise a first light-emitting surface in a display direction. The second color LED comprise a second light-emitting surface in the display direction. An area of the first light-emitting surface is larger than an area of the second light-emitting surface. The shading layer is disposed in the plurality of pixel zones, and the shading layer overlaps some of the first light-emitting surfaces at the display direction.

Abstract: A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment.

Abstract: A wiring configuration tool may be configured to determine a new wiring configuration for a replacement HVAC controller based, at least in part, on the existing wiring configuration for a current HVAC controller and, for example, the make and model of the replacement HVAC controller. The wiring configuration tool may be hosted by a server that provides a user interface for interacting with the user. The user may access the wiring configuration tool via a web services interface, a smart phone application or in any other suitable manner.

Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: A search apparatus receives an input target value, which indicates a condition to be set in a semiconductor processing apparatus or a result obtained by processing the semiconductor using the processing apparatus, a reference value of the condition inside a search area, and the result, wherein the reference value is indicated by the target value. A prediction model indicating a relation between the condition and the result based on a setting value of the condition inside the search area is generated and, a measured value of the result is obtained. A prediction value is acquired by assigning the target value to the prediction model. The prediction value is set to the reference value when it is determined that the prediction value is closer to the target value, and a prediction value satisfying an achievement condition is set when the prediction value satisfies the achievement condition of the target value.

Abstract: A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium which may be used to produce a photomask for manufacturing an integrated circuit.

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

Abstract: One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.

Abstract: A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.

Abstract: An approach for shifting a cut associated with a lineend of an interconnect in a manufacturing system. The approach selects one or more polygons associated with the lineend and determines whether a first cut is spanning the one or more polygons. The approach responds to the first cut does span, determines a presence of a first via on a first interconnect and determines a first distance of the first via to the first cut. The approach determines whether the first distance is greater than a first threshold and responds to the first distance is greater and determines whether the first distance is greater and determines a second distance of the first cut to a second cut. The approach determines whether the second distance is greater than a second threshold and responds to the second distance is greater and generates a shift associated with the first cut and outputs the shift.

Abstract: In an exemplary structure, a first conductor connects a power source to integrated circuit devices. The first conductor includes a first axis defining a first side and a second side. A second conductor, perpendicular to the first conductor, is connected to the first conductor by first vias. A third conductor, parallel to the first conductor, is connected to the second conductor by second vias. The third conductor includes a second axis defining a third side and a fourth side. The first side and the third side are aligned in a first plane perpendicular to the conductors and the second side and the fourth side are aligned in a second plane perpendicular to the conductors. The first vias contact the first conductor in only the first side. The second vias contact the third conductor in only the third side. And the second conductor is outside the second plane.

Abstract: Methods and systems assign an alignment context to each of the cells within an integrated circuit layout, from previously established alignment contexts, based on how the different cell widths cause each of the cells to align with adjoining cells. Also, such methods and systems retrieve standard signal delay times for each of the cells from a standard cell library. This allows these methods and systems to adjust the signal delay times for each of the cells based on which alignment context has been assigned to each of the cells, to produce adjusted delay times for each of the cells. Following this, the methods and systems perform a timing analysis of the layout using the adjusted delay times for each of the cells, and output the results of the timing analysis.

Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Abstract: A layout method is disclosed that includes: placing function cells in a layout, corresponding to at least one design file, of an integrated circuit; and inserting at least one fill cell that is configured without cut pattern to fill at least one empty region between the function cells each comprising at least one cut pattern on at least one edge abutting the at least one empty region.

Abstract: The invention is a method for controlling the activity of two light radiation sources (2, 3) belonging to a stereolithography machine (1) and suited to act at the level of a portion (104) of a superimposition area (101) defined on the work surface (100) of the stereolithography machine (1) for the production of a three-dimensional object (200) through stereolithography. For each one of the lines (210) with generic length L that define each layer (201) of the three-dimensional object (200) within the portion (104), the method provides for activating: a first light radiation source (2) for a first section (211) of the line (210) having length X; a second light radiation source (3) for the remaining second section (212) of the line (210) having length Y, wherein the value X of the first section (211) is selected within the interval 0<=X<=L and wherein Y is calculated as equal to L?X.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.

Abstract: Methods and systems for determining electrically relevant placement of metrology targets using design analysis are disclosed. The method may include: identifying at least one critical design element of an integrated circuit based on a design of the integrated circuit; determining whether the design of the integrated circuit allows for an insertion of a metrology target in a vicinity of the at least one critical design element; and modifying the design of the integrated circuit by inserting a metrology target into the vicinity of the at least one critical design element when the design of the integrated circuit allows for the insertion of the metrology target.

Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.

Abstract: A method of performing virtual connectivity change between first and second nets associated with an integrated circuit is presented. The method includes generating a first top view and a first perspective views of a layout of the integrated circuit when a computer is invoked to perform the virtual connectivity change. The method further includes defining layers associated with the first and second nets, and defining a boundary of the virtual connectivity change. The method further includes performing the virtual connectivity change between the first and second nets within the boundary, and generating a second top view and a second perspective view of the layout of the integrated circuit after the virtual connectivity change.

Abstract: There are provided system and method of generating an examination recipe usable for examining a specimen, the method comprising: capturing images from dies and obtaining noise map indicative of noise distribution on the images; receiving design data representative of a plurality of design groups each having the same design pattern; calculating a group score for each given design group, the group score calculated based on the noise data associated with the given design group and a defect budget allocated for area of the given design group; providing segmentation related to the dies, comprising: associating design groups with segmentation labels indicative of different noise levels based on the group score, thereby obtaining a set of die segments each corresponding to one or more design groups associated with the same segmentation label and segmentation configuration data; and generating an examination recipe using the segmentation configuration data.

Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

Abstract: A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. The schematic design tool computes layout structure data based on the temporary layout and provides the layout structure data to a place and route tool within the design tool system that, in turn, generates a layout based on the layout structure data The design tool system then generates mask layer data based upon the layout that is configured to generate masks for construction of an integrated circuit corresponding to the analog circuit schematic.

Abstract: A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. The method further includes forming a subset of the shapes including the shapes associated with the at least one layout conflict. The method further includes categorizing the shapes of the subset into one of a multitude of topology types, generating stitch candidate solutions for the multitude of topology types, and decomposing the design into a multitude of masks. The subset of the multitude of shapes is formed by generating a first graph representative of the design, decomposing the first graph into at least three colors to form a colored graph; and identifying within the first graph, a second graph including at least one conflict edge.

Abstract: A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow.

Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.

Abstract: A charged particle beam drawing apparatus has a drawing unit including a charged particle source, a deflector and a stage on which a target object is placed, to perform drawing with a charged particle beam on a plurality of drawing regions on the target object, and a calculator to calculate a drawing progress ratio on the target object using a ratio of a drawn area of the drawing regions to a total area of the drawing regions.

Abstract: A method, of seeding an optical proximity correction (OPC) process, includes: receiving, at an input device of a computer, a subject pre-OPC design-signature for a subject pre-OPC design package; selecting, by the processor and via interaction with an OPC database operatively connected to the computer, one amongst archived post-OPC design packages based on relatedness between the subject pre-OPC design-signature and archived post-OPC design-signatures corresponding to the archived post-OPC design packages, and thereby retrieving the selected archived post-OPC design packages; and generating one or more seeds for the OPC process based on the selected archived post-OPC design package.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.

Abstract: According to one embodiment, a guide pattern data correcting method is for correcting guide pattern data of a physical guide for formation of a polymer material to be microphase-separated. The physical guide has a plurality of concave portions in the guide pattern data, and at least two concave portions out of the plurality of concave portions are connected to each other. The guide pattern data is subjected to correction by shifting or rotation of at least either of the two connected concave portions.

Abstract: In a system for facilitating mesh generation corresponding to a volumetric, prismatic object, generalized polyhedrons representing at least a portion of a layer of the volumetric object are transformed into a set of convex polyhedrons based on, at least in part, the prismatic properties of the volumetric object. The convex polyhedrons corresponding to a layer are decomposed into a set of tetrahedrons by accounting for an intersecting and/or overlapping edge of a polyhedron in an adjacent layer, so that the set of tetrahedrons automatically, i.e., without having to enforce any continuity requirements after tetrahedron generation, forms a mesh of that is continuous with tetrahedrons corresponding to the adjacent layer.

Abstract: A method of displaying a plurality of graphical user interface elements, each graphical user interface element representing a step in a measurement design, setup and/or monitoring process and each graphical user interface element enabling access by the user to further steps in the measurement design, setup and/or monitoring process for the associated step of the graphical user interface element, and displaying an indicator associated with one or more of the plurality of graphical user elements, the indicator indicating that a step in the measurement design, setup and/or monitoring process is not completed and/or that a key performance indicator associated with a step in the measurement design, setup and/or monitoring process has passed a threshold.

Abstract: A method is disclosed that includes determining whether there is a conflict graph representing that each spacing between any two of at least five adjacent patterns of multiple-patterning patterns of a layout of an integrated circuit (IC) is less than a threshold spacing, and if there is the conflict graph, modifying the multiple-patterning patterns to exclude patterns represented by the conflict graph, for fabrication of the IC.

Abstract: A MMIC (microwave monolithic integrated circuit) based FET mixer and method for the same is provided. In particular, adjacent transistors, such as FETs (field effect transistors) share terminals reducing physical layout separation and interconnections. A smaller die size is realized with the improved system geometry herein provided.

Abstract: A method of manufacturing a substrate is disclosed. The method includes receiving a plurality of pixel elements, wherein each of the pixel elements includes data members; and transferring the data members to a plurality of exposing devices that are configured to conditionally expose the substrate with an incident energy beam when coupled with the data members, wherein different data members of one pixel element are transferred at different system cycles.

Abstract: A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-Synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells for the integrated circuit. The method may further include determining, using a cross-probe criterion, an amount of cross-correlation between a first cell and a second cell in the gate-level netlist. The method may further include generating, in response to the amount of cross-correlation exceeding a correlation threshold, a cell group including the first cell and the second cell. The method may further include determining a boundary condition for the cell group. The method may further include generating a floorplan. The first cell and the second cell may be placed in the floorplan according to the boundary condition.

Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to the edge of the first external dummy is greater than a first distance.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Abstract: An IC design method includes: receiving a first layout including a first pattern; receiving a second layout including a second pattern, the first pattern separated from the second pattern when overlapping the first layout and the second layout; providing a cut pattern between the first pattern and the second pattern and overlapping the first pattern when overlapping the first layout, the second layout and the cut pattern; and providing a jog extending from the cut pattern to further overlap the first pattern with a length when a spacing between the second pattern and an edge of the cut pattern overlapping the first pattern is lower than a predetermined value, in which a ratio of the length of the jog to the spacing between the second pattern and the edge of the cut pattern overlapping the first pattern is in a range of 1/5 to 1/1.

Abstract: In one aspect, a CAD-based method for designing a lithographic mask for nanowire-based devices is provided which includes the steps of: create a design for the mask from existing (e.g., FINFET or planar CMOS) design data which includes, for each of the devices, one or more nanowire mask shapes (FINFET design data) or continuous shapes (planar CMOS design data); for FINFET design data, merging the nanowire mask shapes into continuous shapes; expanding the continuous shapes to join all of the continuous shapes in the design together forming a single polygon shape; removing the continuous shapes from the single polygon shape resulting in landing pad shapes for anchoring the nanowire mask shapes; for CMOS design data, dividing the continuous active shapes into one or more nanowire mask shapes; and merging the landing pad shapes with the nanowire mask shapes to form the lithographic mask.

Abstract: Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.