Including Instrumentation And Profiling Patents (Class 717/158)
  • Patent number: 11550700
    Abstract: Disclosed are implementations for software debugging and application development, including a method that includes receiving an instrumentation request, associated with one or more contextual conditions, for application data resulting from execution of an application process on an application system, the application process corresponding to source code with a segment to capture data at a first observability level. The instrumentation request includes information to cause adjustment of the first observability level to a second observability level different from the first observability level.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: January 10, 2023
    Assignee: Lightrun Platform LTD
    Inventors: Leonid Blouvshtein, Ilan Peleg
  • Patent number: 11537403
    Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: December 27, 2022
    Assignee: INTEL CORPORATION
    Inventors: Subramaniam M. Maiyuran, Guei-Yuan Lueh, Supratim Pal, Gang Chen, Ananda V. Kommaraju, Joy Chandra, Altug Koker, Prasoonkumar Surti, David Puffer, Hong Bin Liao, Joydeep Ray, Abhishek R. Appu, Ankur N. Shah, Travis T. Schluessler, Jonathan Kennedy, Devan Burke
  • Patent number: 11520689
    Abstract: One embodiment provides a system for automatic program repair (APR). The system identifies a first set of components under repair in a software system and determines, while executing an original test, second and third sets of components that are executed before and after, respectively, the first set of components. The system generates a first block of mock code that runs faster and simulates runtime behaviors of the second set of components, identifies a code region within the third set of components that affects a test result of the software system, and generates a second block of mock code that runs faster and affects the test result similarly. The system generates a fast-result test by replacing the second set of components with the first block of mock code and replacing the third set of components with the second block of mock code and performs APR by executing the fast-result test.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 6, 2022
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eric A. Bier, Alexandre Campos Perez
  • Patent number: 11512963
    Abstract: Embodiments are directed to a system and methods for ingesting location event data and encoding location data in the event data to a proximity. The encoding includes geohashing latitude and longitude for each event to a proximity for analysis and throughput.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 29, 2022
    Assignee: Wejo Ltd.
    Inventors: Alan Gawthorpe, Roger Downing
  • Patent number: 11483211
    Abstract: A method, a computer program product, and a system for infrastructure discovery and service offering. The method includes discovering configuration information of components on an IT infrastructure of an enterprise. The method also includes discovering components, resources, and workload characteristics based on the configuration information. The method further includes analyzing the configuration information, components, resources, and workload characteristics to determine predictive need analytics and discovering applications operating within the IT infrastructure. The method also includes comparing the applications and predictive need analytics to cloud-based services to detect service compatibilities, and generating a decision-making chart based on the service compatibilities, wherein the decision-making chart indicates migratable components and applications in the IT infrastructure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Madhu Akhilesham, Venkata Vara Prasad Karri, Akash U. Dhoot, Niteen D Lakhe, Shailendra Moyal
  • Patent number: 11397580
    Abstract: Methods, devices and media for reducing register pressure in flexible vector processors are described. In various embodiments described herein, methods, devices and media are disclosed that selectively re-scalarize vector instructions in a sequence of instructions such that register pressure is reduced and thread level parallelism is increased. A compiler may be used to perform a first method to partially or fully scalarize vectorized instructions of a code region of high register pressure. A compiler may be used to perform a second method to fully scalarize a sequence of vectorized instructions while preserving associations of the scalar instructions with their original vectorized instructions; the scalar instructions may then be scheduled and selectively re-vectorized. Devices executing code compiled with either method are described, as are processor-readable media storing code compiled by either method.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: July 26, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ahmed Mohammed ElShafiey Mohammed Eltantawy, Ning Xie
  • Patent number: 11385983
    Abstract: An approach is provided for implementing memory profiling aggregation. A hardware aggregator provides memory profiling aggregation by controlling the execution of a plurality of hardware profilers that monitor memory performance in a system. For each hardware profiler of the plurality of hardware profilers, a hardware counter value is compared to a threshold value. When a threshold value is satisfied, execution of a respective hardware profiler of the plurality of hardware profilers is initiated to monitor memory performance. Multiple hardware profilers of the plurality of hardware profilers may execute concurrently and each generate a result counter value. The result counter values generated by each hardware profiler of the plurality of hardware profilers are aggregated to generate an aggregate result counter value. The aggregate result counter value is stored in memory that is accessible by a software processes for use in optimizing memory-management policy decisions.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: July 12, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Sergey Blagodurov, Jinyoung Choi
  • Patent number: 11354054
    Abstract: Compaction of an ordered event stream (OES) is disclosed. An OES storage system can employing multiple tiers of storage devices, wherein the different tiers each can provide certain advantages and disadvantages that can be used to balance OES event storage costs, both monetarily and in terms of computing resource burden. Compaction can be facilitated by storing, in a stream map, a reference to an event stored via a second tier of storage in contrast to storing in the stream map actual events of a first tier of storage. A reference can be enabled by storing events in a chunk body and storing a location relationships in a header of the chunk. The stream map can then search headers for references, which can often be smaller than the events themselves, which references can then be communicated, stored, and updated in the stream map to facilitate OES compaction.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: June 7, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Andrei Paduroiu
  • Patent number: 11275672
    Abstract: Techniques are disclosed for determining the run-time performance of an application executing on a computing system with low impact on the performance of the computing system. For example, a time series telemetry data stream is obtained for each of a plurality of key performance indicators during run-time execution of the application on a computing system having a given system configuration. One or more statistical features are extracted from each time series telemetry data stream. Model parameters of a machine learning performance score model are populated with values of the extracted statistical features. A run-time performance score of the application is then determined using the model parameters of the machine learning performance score model populated with the values of the extracted statistical features.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: March 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Farzad Khosrowpour, Amihai Savir, Anat Parush Tzur
  • Patent number: 11269988
    Abstract: An automated application verification module is provided to identify one or more functions of a software application. There is added, for at least one of the identified functions, a verification prologue at the entry point of the function which does not alter the control flow of the original set of instructions of the function and/or does not change the semantics of the function when the verification prologue is executed in its entirety. There is added at least one corresponding verification prologue check to the software application, such that the verification prologue check is configured to automatically check the integrity of the corresponding verification prologue during execution of the software application.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 8, 2022
    Assignee: PNC BUSINESS CREDIT
    Inventor: Sander Bogaert
  • Patent number: 11270406
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Patent number: 11265145
    Abstract: The disclosure concerns implementing, by a cryptographic circuit, a set of substitution operations of a cryptographic process involving a plurality of substitution tables. For each set of substitution operations of the cryptographic process, a series of sets of substitution operations are performed. One set of the series is a real set of substitution operations corresponding to the set of substitution operations of the cryptographic process. One or more other sets are dummy sets of substitution operations, each dummy set being based on a different permutation of said substitution tables.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 1, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Yanis Linge, Thomas Ordas, Pierre-Yvan Liardet
  • Patent number: 11265423
    Abstract: Apparatus and methods are disclosed for display-related analysis of call data in an IPBX. In an example embodiment, an apparatus is configured to route data/VoIP calls via a data-communications server. An interface circuit is configured to selected parameters of interest based on capabilities of a set of devices and generate subscription requests to subscribe the devices to the parameters of interest. A processing circuit is configured to generate call summary metrics from call event messages for calls routed by the server and with subscription requests being associated with the parameters of interest. The call summary metrics are evaluated in connection with the parameters of interest as subscribed to by the devices and results of the evaluation are provided to the communication devices.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 1, 2022
    Assignee: 8x8, Inc.
    Inventors: Zhishen Liu, Qing Zhao
  • Patent number: 11263602
    Abstract: Embodiments allocate and synchronize virtual currency balance of a user among multiple user devices. A user profile is maintained at a central server. The user profile stores a total virtual currency balance and a designation of multiple user devices associated with the user. The total virtual currency balance may be divided among and allocated to the multiple user devices, for example, based on usage data associated with each user device. The portion of the total virtual currency balance allocated to each user device may be stored locally at a local wallet of the corresponding user device. The local virtual currency balance on a user device may be used to purchase goods or services, such as playing a game. If the locally stored virtual currency balance of a given user device runs low, the user device may request additional virtual currency from other user devices without contacting the central server.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 1, 2022
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventor: Zhiqiang Zhang
  • Patent number: 11221834
    Abstract: Systems and methods for auto-tuning and compiling source code are provided. A first executable file is generated by compiling the source code in accordance with a first optimization scheme. Compiling reports, performance reports, and bottleneck information are generated for the first executable file. A second optimization scheme is generated, and a second executable file is generated by compiling the source code in accordance with the second optimization scheme. An optimized executable file is output based on the first executable file and the second executable file.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: January 11, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yaoqing Gao, Xuan Zhong, Peng Wu, Long Chen
  • Patent number: 11221920
    Abstract: Methods and systems for backing up and restoring sets of electronic files using sets of pseudo-virtual disks are described. The sets of electronic files may be sourced from or be stored using one or more different data sources including one or more real machines and/or one or more virtual machines. A first snapshot of the sets of electronic files may be aggregated from the different data sources and stored using a first pseudo-virtual disk. A second snapshot of the sets of electronic files may be aggregated from the different data sources subsequent to the generation of the first pseudo-virtual disk and stored using the first pseudo-virtual disk or a second pseudo-virtual disk different from the first pseudo-virtual disk.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: January 11, 2022
    Assignee: RUBRIK, INC.
    Inventor: Soham Mazumdar
  • Patent number: 11218291
    Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: January 4, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Thomas Ordas, Yanis Linge
  • Patent number: 11194612
    Abstract: This disclosure provides a solution for improving performance in a virtual machine. In this method, a platform independent intermediate representation of a code segment in an application is obtained from a first virtual machine which is operating on a first platform. The platform independent intermediate representation is generated through a run-time compilation by the first virtual machine. Native code is generated based on the platform independent intermediate representation, in which at least one piece of the native code corresponds to a second platform which is different from the first platform. The at least one piece of the native code is distributed to a second virtual machine which is operating on the second platform.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ting Wang, Xiao Ping Guo, Xiao Lei Hu, Yang Liu, Dan Liu, Ning Zhao
  • Patent number: 11188314
    Abstract: Systems and methods for auto-tuning and compiling source code are provided. A first executable file is generated by compiling the source code in accordance with a first optimization scheme. Compiling reports, performance reports, and bottleneck information are generated for the first executable file. A second optimization scheme is generated, and a second executable file is generated by compiling the source code in accordance with the second optimization scheme. An optimized executable file is output based on the first executable file and the second executable file.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 30, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yaoqing Gao, Xuan Zhong, Peng Wu, Long Chen
  • Patent number: 11188315
    Abstract: The disclosed systems, apparatuses and methods are directed to optimizing by a compiler register resource allocation for functions of a module, using a Register File comprising a limited number of registers. After performing interprocedural analysis in the module, the compiler computes the number of registers used by each function, and compiles the function to final machine code, except at callsites where a call is detected to be made to another function. At each callsite and for each called function, the compiler expands call instructions to final machine code after computing and setting a relative index to be used by a called function for running in an available part of the Register File. The relative index optimizes register resource allocation by minimizing the number of spilled registers before a function is called.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: November 30, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yan Luo, Ahmed Mohammed ElShafiey Mohammed Eltantawy, Tyler Bryce Nowicki
  • Patent number: 11188364
    Abstract: A method list is built for a currently executing application within a process virtual machine at a snapshot point, the method list comprising a set of methods capable of being executed by the currently executing application after the snapshot point, the snapshot point comprising an execution state of the currently executing application when a snapshot process is triggered. Profiling data of the currently executing application, collected prior to reaching the snapshot point, is committed, to a designated storage location. Using the profiling data and a just-in-time compiler of the process virtual machine, a method in the method list is compiled. Snapshot data comprising data of the execution state of the currently executing application at the snapshot point, including a result of the compiling, is stored.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vijay Sundaresan, Mark Graham Stoodley, Andrew James Craik, Daniel Heidinga, Ashutosh Mehra
  • Patent number: 11163645
    Abstract: A computer device includes a memory. The computer device also includes at least one processor configured to execute a process and manage the memory for the process. The processor is further configured to execute one or more program instructions associated with an application, reach control flow transfer for the one or more program instructions, unwind a call stack associated with the one or more program instructions in response to a failure to meet a target control flow, identify an offending function call, and rewrite the offending function call. The rewritten function call includes a memory operation boundary check.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 2, 2021
    Inventors: Ameer Kashani, Gopalakrishnan Iyer
  • Patent number: 11157252
    Abstract: A method, computer system, and computer program product for estimation of post-inlining transformation benefits are provided. The embodiment may include performing abstract interpretation on a program to find potential post-inlining transformations. The embodiment may also include encoding potential post-inlining transformations into a profitability metric by associating constraints under which a profit is determined to be realized. The embodiment may further include scaling the profitability metric using the relative execution frequency of the program point to which the transformation applies to favor applying transformations in the most frequently executed code paths. The embodiment may also include generating method summaries to store the potential post-inlining transformations in the method summaries. The embodiment may further include creating a method summary map to match each method with each method summary.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew James Craik, Erick Ochoa, Jose Nelson Amaral, Karim Ali
  • Patent number: 11138018
    Abstract: Profile-guided optimization is a technique for optimizing execution of computer programs using profile information to improve program runtime performance. Obtaining the profile information can be challenging, especially in live production environments such as high-performance gaming systems. A profiling strategy is provided herein that obtains profile information without requiring extra effort from users. The profiling strategy collects several approximate, lightweight profiles called piecemeal profiles over one or more lifetimes of a computer program, or application. The piecemeal profiles are then used to generate whole program application profiles that can then be used to improve the execution of the application. A piecemeal profile is profile information of a section or portion of an application.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 5, 2021
    Assignee: Nvidia Corporation
    Inventors: Marc Blackstein, Ram Rangan
  • Patent number: 11113610
    Abstract: A system and related method for building and deploying one or more inference models for use in remote condition monitoring of a first fleet of a first asset. The system includes model configuration data for subsequent use by a model builder application to construct one or more desired inference models for the first asset. The model configuration data is customized to the first asset and the desired one or more inference models, and is provided in a format which is easily readable and editable by a user of the system. The model configuration data is separate from the underlying processing algorithms which are employed by the model builder application in the constructing of the one or more desired inference models during a learning mode of operation of the system.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: September 7, 2021
    Inventors: Donna Louise Green, Brian David Larder, Peter Robin Knight, Olivier Thuong
  • Patent number: 11112845
    Abstract: A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 7, 2021
    Assignees: National Taiwan University, MFDIATEK INC.
    Inventors: Wen-Li Shih, Jenq-Kuen Lee, Cheng-Yen Lin, Ming-Yu Hung
  • Patent number: 11106439
    Abstract: An offload server includes: a parallel processing designation section configured to identify repeat statements in an application and specify a directive specifying application of parallel processing by an accelerator and perform compilation for each of the repeat statements; a parallel processing pattern creation section configured to create parallel processing patterns each of which specifies whether to perform parallel processing for repeat statements not causing a compilation error; a performance measurement section configured to compile the application with a parallel processing pattern, deploy the compiled application to a verification machine, and perform processing for a measurement of a performance of the application; and an executable file creation section configured to compile a parallel processing pattern with the highest processing performance to create an executable file.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 31, 2021
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yoji Yamato, Tatsuya Demizu, Hirofumi Noguchi, Misao Kataoka
  • Patent number: 11013994
    Abstract: The invention discloses how even underdeveloped regions can be provided with telecommnunication terminals (mobile terminals, tablets, laptops) using little computing power of the telecommunication terminals, thus allowing a participation in the exchange of digital information.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 25, 2021
    Inventors: Frederik Peter, Sheikh Khalil, Remco Westermann
  • Patent number: 10860299
    Abstract: Data transformation in a distributed system of applications and data repositories is described. The subsystems for the overall framework are distributed, thereby allowing for customization to require only isolated changes to one or more subsystems. In one embodiment, a source code repository is used to receive and store source code. A build subsystem can retrieve source code from the source code repository and build it, using one or more criteria. By building the source code, the build subsystem can generate an artifact, which is executable code, such as a JAR or SQL file. Likewise, by building the source code, the build subsystem can generate one or more job specifications for executing the executable code. In one embodiment, the artifact and job specification may be used to launch an application server in a cluster. The application server can then receive data transformation instructions and execute the data transformation instructions.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 8, 2020
    Assignee: Palantir Technologies Inc.
    Inventors: Robert Fink, Matthew Cheah, Mingyu Kim, Lynn Cuthriell, Divyanshu Arora, Justin Uang, Jared Newman, Jakob Juelich, Kevin Chen, Mark Elliot, Michael Nazario
  • Patent number: 10846437
    Abstract: System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter is the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Anatoli Bolotov, Mikhail Grinchuk
  • Patent number: 10838971
    Abstract: Embodiments of an informatics platform where collected data can be normalized, integrated and mapped to a knowledge source, such as medical vocabulary systems are disclosed. One example of such a knowledge source is Unified Medical Language System (UMLS) which is a knowledge source for biomedical applications. Embodiments as depicted herein may provided a method to convert the desired information from UMLS into an ontology representation to allow for its use in conjunction with an informatics system.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: November 17, 2020
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventor: Parsa Mirhaji
  • Patent number: 10805377
    Abstract: A computing device having connectivity to a network stores one or more existing device models, where each of the one or more existing device models is a representation of a different client device used by a first authenticated user to access the network. The computing device obtains a device sample, which comprises network traffic data that is captured during a period of time and which is generated by a particular client device associated with the authenticated user of the network. The computing device determines, based on one or more relational criteria, whether the device sample should be assigned to one of the one or more existing device models or to an additional device model that has not yet been created. The computing device then determines relative identity of the particular client device based on whether the device sample is assigned to one of the one or more device models or to an additional device model that has not yet been created.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 13, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Martin Grill, Jan Kohout, Martin Kopp
  • Patent number: 10725751
    Abstract: A method, apparatus, and/or computer program product generates a predictive data structure for an application when operating offline in a network connected data processing system, the application comprising source code having an execution path. The method comprises: determining an exit point within the source code of the application; determining, from the exit point, an execution path comprising at least one conditional statement; identifying one or more branches of the at least one identified conditional statement and for each identified branch determining an expected response; for each determined expected response, generating a data structure from the response; continuing along the execution path of the source code from the exit point and replacing each request for a resource in the source code with a pointer to the generated data structure; and executing the source code with the pointer to the generated data structure from the determined exit point.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventor: Benjamin J. Fletcher
  • Patent number: 10719431
    Abstract: Techniques are described for graph based code performance analysis of software, such as software that is being developed and tested in a development environment. Implementations provide a technique for instrumenting code by adding various annotations into the code. Each annotation may be a function call that executes with the annotated code, but does not alter the behavior and/or functionality of the annotated code apart from outputting call tracking information during execution. The call tracking information generated by annotations can be analyzed to generate a call graph that depicts calling relationships between functions in the code. The call graph can be presented within a user interface and/or automatically analyzed to develop recommendations regarding code coverage for testing, impact information describing how changes to one function impact another function, code optimization recommendations, and so forth.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 21, 2020
    Assignee: SAP SE
    Inventors: Yang Peng, Yueling Wang, Jieying Zhang, Yunfeng Jiang, Junshan Xu
  • Patent number: 10698894
    Abstract: Described herein are technologies relating to including instrumentation code in enterprise pages and generating a report for an enterprise page based upon instrumentation data and organizational data. Instrumentation code in an enterprise page, when executed by a processor, causes the processor to generate instrumentation data, where the instrumentation data includes an identifier for the enterprise page and an identifier for a user who accessed the enterprise page. The instrumentation data is added to an instrumentation dataset. A report is generated for an enterprise page based upon the instrumentation data and organizational data, such that the report indicates how users across different sectors of the enterprise interact with the enterprise page.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 30, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Swapnil Palod, Sriram Kakara, Mark Saroufim
  • Patent number: 10693798
    Abstract: A system receives an incoming datastream at an incoming data rate or transmits an outgoing datastream at an outgoing data rate. The system may include a detection circuit to monitor the signal quality of the datastream. Responsive to changes in the monitored signal quality, the system may switch the data rate from a first data rate to a new data rate. If signal conditions are favorable, the system may switch to a higher data rate than the first data rate. If signal quality conditions worsen, the system may switch from the first data rate to a lower data rate to allow for a reduction in error rate.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: June 23, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventor: German Stefan Otto Feyh
  • Patent number: 10691430
    Abstract: An apparatus to facilitate instruction scheduling is disclosed. The apparatus includes one or more processors to receive a block of instructions, divide the block of instructions into a plurality of sub-blocks based on a register pressure bounded by a predetermined threshold and instructions in each of the plurality of sub-blocks for processing.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Wei Pan, Wei-Yu Chen, Guei-Yuan Lueh
  • Patent number: 10678910
    Abstract: Examples disclosed herein relate to modifying a web page. In one example, in response to beginning execution of a process initiating generation of a web page of a web application at a server, a runtime agent is executed. In this example, the runtime agent modifies code of the web page to inject code to protect output of the web page. In the example, the process can be executed using the modified code to generate a modified web page.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: June 9, 2020
    Assignee: Micro Focus LLC
    Inventors: Ming Sum Sam Ng, Alvaro Munoz, Oleksandr Mirosh
  • Patent number: 10565133
    Abstract: Methods and apparatus for reducing accelerator-memory access costs in platforms with multiple memory channels. The apparatus includes a computing platform having multiple accelerators and multiple memory devices accessed via a plurality of memory channels. Jobs are submitted via software running on the computing platform to access a function to be offloaded to an accelerator. Under the offloaded function, the accelerator accesses one or more buffers that collectively requiring access via multiple memory channels among the plurality of memory channels. Accelerators having an available instance of the function are identified, and an aggregate cost for accessing the one or more buffers via the multiple memory channels are calculated for each of the accelerators. The accelerator with the least aggregate cost is then selected to offload the function to. New Instruction Set Architecture (ISA) instructions are also disclosed to identify memory pages and memory channels used for buffers.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventor: Vinodh Gopal
  • Patent number: 10467117
    Abstract: Techniques for providing application contextual information. One or more sets of database context identifiers corresponding to events that occur within the database are generated by the database. The one or more sets of database context identifiers have at least one application context field. A session identifier corresponding to a session to be monitored is sent from the application to the database. Information to be stored in the database with the session identifier is sent to the database. Database logs and application logs are correlated using at least the session identifier.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 5, 2019
    Assignee: salesforce.com, inc.
    Inventor: Mark Wilding
  • Patent number: 10462748
    Abstract: A method and system for energy savings with silent haptics is presented. A haptically-enabled device includes a processor that executes a haptic track containing haptic instructions. The haptic track is analyzed to determine the presence of a zero-force interval, also known as a silent haptic. The duration of the zero-force interval is determined, and if the duration exceeds a pre-determined threshold, then the system or method enters an energy savings mode. An overhead time associated with the terminating of the energy savings mode is determined. And, the energy savings mode is terminated at the conclusion of the zero-force interval less the overhead time.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 29, 2019
    Assignee: IMMERSION CORPORATION
    Inventors: Henry Da Costa, Yoshiaki Date
  • Patent number: 10445494
    Abstract: In one embodiment, a processor comprises: a first register to store a first bound value for a stack to be stored in a memory; a second register to store a second bound value for the stack; a checker logic to determine, prior to an exit point at a conclusion of a function to be executed on the processor, whether a value of a stack pointer is within a range between the first bound value and the second bound value; and a logic to prevent a return to a caller of the function if the stack pointer value is not within the range. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Ravi L. Sahita, Yuriy Bulygin, Xiaoning Li, Jason W. Brandt
  • Patent number: 10419483
    Abstract: A system and method for generating remediated instructions that complies with one or more policies that specify constraints for computer executable instructions. The remediated instructions are generated based at least in part on an evaluation of a set of straight-line paths of the set of executable instructions and an execution flow for the set of straight-line paths.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: September 17, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Nicholas Alexander Allen
  • Patent number: 10409701
    Abstract: One or more client threads are executed. One or more processing threads corresponding to the one or more client threads are executed. The processing threads are configurable to generate statistical information for each database query statement processed by the corresponding client thread. The statistical information is generated from the processing threads. The statistical information is stored in chunks of memory managed via a plurality of queues. The chunks of memory containing the statistics are analyzed. Outlier statements are filtered based on the statistics. Non-outlier statements are stored by a storage device.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: September 10, 2019
    Assignee: salesforce.com, inc.
    Inventor: Mark Wilding
  • Patent number: 10353859
    Abstract: A method for allocating registers in a compute unit of a vector processor includes determining a maximum number of registers that are to be used concurrently by a plurality of threads of a kernel at the compute unit. The method further includes setting a mode of register allocation at the compute unit based on a comparison of the determined maximum number of registers and a total number of physical registers implemented at the compute unit.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: July 16, 2019
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: YunPeng Zhu, Jimshed Mirza
  • Patent number: 10296323
    Abstract: A system and method for deploying user apps to user devices is disclosed. A service module on a host system maintains class files of the user app within an original archive, and creates an install agent archive and a modified user app archive from the original archive. In some embodiments, the service module deploys an install agent from the install agent archive and a runtime agent of the modified user app archive to the user device. In other embodiments, the install agent and the runtime agent are pre-installed within a virtual machine of the user device. The install agent receives the class files from the service module, and the runtime agent loads and executes the class files to deploy the user app on the user device. In a preferred embodiment, the system enables faster initial deployment and redeployment of user apps on Android user devices than current systems and methods.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 21, 2019
    Assignee: Zeroturnaround AS
    Inventors: Madis Pink, Allan Raundahl Gregersen, Rein Raudjärv
  • Patent number: 10289842
    Abstract: An apparatus and a method for protecting kernel control-flow integrity using static binary instrumentation are provided. The method includes configuring a compiler to reserve a register in a processor, compiling source code into a binary based on the configured compiler, and modifying the binary to prevent exploits using the reserved register, wherein the reserved register stores a first encryption key for encrypting and decrypting return addresses. The reserved register stores an encryption key that is used to encrypt and decrypt return addresses to prevent control flow exploits.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: James Gleeson, Ahmed Azab, Wenbo Shen, Rohan Bhutkar
  • Patent number: 10268454
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector load operations. An example apparatus includes a node grouper to associate a vector operation with a node group, a candidate verifier to perform a dependencies test on a subset of the node group, and identify a subset of the node group as a candidate when the subset satisfies the dependencies test, and a code optimizer to determine replacement code based on a characteristic of the candidate in the node group and compare an estimated cost associated with executing the replacement code to a threshold. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Farhana Aleen Schuchman, David L. Kreitzer, Rakesh Krishnaiyer, Vyacheslav Pavlovich Zakharin, Sergey Preis, Leonardo Jose Borges, Philippe Thierry
  • Patent number: 10261806
    Abstract: A computer-implemented method uses a predictive time-sequence model to adapt hardware configurations at run-time for an application including multiple stages of execution. At each stage a system monitor is started at the launch of a first task in a first run to collect performance data. The system monitor is stopped at the completion of a last task in the first run, then a predictive optimal configuration is computed and applied to the remaining runs in the stage.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: J. I. Azhen, Yi Ge, Yong Hua Lin, Chao Xue, Rong Yan
  • Patent number: 10261766
    Abstract: A system, method, and a computer-readable storage device for sloppy feedback loop compilation are described herein. For example, a dataflow application definition can be obtained. The dataflow application definition may include a feedback loop bounding a compute block. It may then be determined that the feedback loop is to be compiled as a sloppy feedback loop. The dataflow application can then be compiled as an executable object that pipelines the compute block of the dataflow application.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 16, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: Benjamin Orth Chandler