Single Electron Transistor Patents (Class 977/937)
  • Patent number: 9029936
    Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Patent number: 8519505
    Abstract: An electrically conductive composite material that includes an electrically conductive polymer, and at least one metal nanoparticle coated with a protective agent, wherein said protective agent includes a compound having a first part that has at least part of the molecular backbone of said electrically conductive polymer and a second part that interacts with said at least one metal nanoparticle.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: August 27, 2013
    Assignee: 3M Innovative Properties Company
    Inventors: Yuji Hiroshige, Hidekl Minami, Norihisa Watanabe, Jun Fujita
  • Patent number: 8421060
    Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 16, 2013
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyun Cheol Koo, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim, Jang Hae Ku
  • Publication number: 20120286243
    Abstract: A field-effect transistor or a single electron transistor is used as sensors for detecting a detection target such as a biological compound. A substrate has a first side and a second side, the second side being opposed to the first side. A source electrode is disposed on the first side of the substrate and a drain electrode disposed on the first side of the substrate, and a channel forms a current path between the source electrode and the drain electrode. An interaction-sensing gate is disposed on the second side of the substrate, the interaction-sensing gate having a specific substance that is capable of selectively interacting with the detection target. A gate for applying a gate voltage adjusts a characteristic of the transistor as the detection target changes the characteristic of the transistor when interacting with the specific substance.
    Type: Application
    Filed: July 24, 2012
    Publication date: November 15, 2012
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Patent number: 8299520
    Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
  • Patent number: 8288754
    Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to a
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: October 16, 2012
    Assignees: NXP B.V., ST MicroElectronics (Crolles 2) SAS
    Inventors: Gregory Bidal, Frederic Boeuf, Nicolas Loubet
  • Patent number: 8232561
    Abstract: Embodiments of the invention relate to vertical field effect transistor that is a light emitting transistor. The light emitting transistor incorporates a gate electrode for providing a gate field, a first electrode comprising a dilute nanotube network for injecting a charge, a second electrode for injecting a complementary charge, and an electroluminescent semiconductor layer disposed intermediate the nanotube network and the electron injecting layer. The charge injection is modulated by the gate field. The holes and electrons, combine to form photons, thereby causing the electroluminescent semiconductor layer to emit visible light. In other embodiments of the invention a vertical field effect transistor that employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 31, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Andrew Gabriel Rinzler, Bo Liu, Mitchell Austin McCarthy, John Robert Reynolds, Franky So
  • Patent number: 8232165
    Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Lidija Sekaric
  • Patent number: 8158538
    Abstract: The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor operating at room temperature and a method of manufacturing the same, which are capable of minimizing influence of the gate voltage on tunneling barriers and effectively controlling the electric potential of a quantum dot (QD), by forming the quantum dot using a trenched nano-wire structure and forming the gate to wrap most of the way around the quantum dot.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 17, 2012
    Assignee: Nanochips, Inc.
    Inventors: Jung Bum Choi, Seung Jun Shin
  • Patent number: 8143658
    Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: March 27, 2012
    Assignee: QuNano AB
    Inventors: Lars Samuelson, Claes Thelander
  • Patent number: 8124961
    Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
  • Patent number: 8120015
    Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: February 21, 2012
    Assignees: Samsung Electronics Co., Ltd., Korea University Industrial and Academic Collaboration Foundation
    Inventors: Yun-Kwon Park, Sung-Woo Hwang, Jea-Shik Shin, Byeoung-Ju Ha, Jae-Sung Rieh, In-Sang Song, Yong-Kyu Kim, Byeong-Kwon Ju, Hee-Tae Kim
  • Patent number: 8026508
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 27, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Myung-Sim Jun, Moon-Gyu Jang, Tae-Gon Noh, Tae-Moon Roh
  • Patent number: 8017935
    Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Renaldi Winoto, Dirk Leipold
  • Patent number: 7955932
    Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
  • Publication number: 20110042648
    Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.
    Type: Application
    Filed: January 8, 2010
    Publication date: February 24, 2011
    Inventors: Hyun Cheol Koo, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim, Jang Hae Ku
  • Patent number: 7880162
    Abstract: A quantum dot (22) is formed on a GaAs substrate (20). In the quantum dot (22), a single electron exists. A cap layer (26) is formed on a surrounding area of the quantum dot (22), and a barrier layer (28) is formed thereon. A quantum dot (30) for detection is formed on the barrier layer (28). Then, a cap layer (34) covering the quantum dot (30) and the like is formed.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: February 1, 2011
    Assignee: Fujitsu Limited
    Inventor: Haizhi Song
  • Publication number: 20100327260
    Abstract: The present invention relates to a single electron transistor operating at room temperature and a manufacturing method for same. More particularly, the present invention relates to a single electron transistor operating at room temperature, in which a quantum dot or a silicide quantum dot using a nanostructure is formed and a gate is positioned on the quantum dot so as to minimize influence on a tunneling barrier and achieve improved effectiveness in electric potential control for the quantum dot and operating efficiency of the transistor, and a manufacturing method for same.
    Type: Application
    Filed: February 13, 2009
    Publication date: December 30, 2010
    Applicant: Chungbuk National University Industry-Academic Cooperation Foundation
    Inventors: Jung Bum Choi, Seung Jun Shin
  • Patent number: 7767995
    Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: August 3, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Renaldi Winoto, Dirk Leipold
  • Patent number: 7749922
    Abstract: The present invention provides structures and devices comprising conductive segments and conductance constricting segments of a nanowire, such as metallic, superconducting or semiconducting nanowire. The present invention provides structures and devices comprising conductive nanowire segments and conductance constricting nanowire segments having accurately selected phases including crystalline and amorphous states, compositions, morphologies and physical dimensions, including selected cross sectional dimensions, shapes and lengths along the length of a nanowire. Further, the present invention provides methods of processing nanowires capable of patterning a nanowire to form a plurality of conductance constricting segments having selected positions along the length of a nanowire, including conductance constricting segments having reduced cross sectional dimensions and conductance constricting segments comprising one or more insulating materials such as metal oxides.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: July 6, 2010
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Alexey Bezryadin, Mikas Remeika
  • Publication number: 20100155703
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.
    Type: Application
    Filed: July 7, 2009
    Publication date: June 24, 2010
    Inventors: Myung-Sim JUN, Moon-Gyu JANG, Tae-Gon NOH, Tae-Moon ROH
  • Patent number: 7633148
    Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: December 15, 2009
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Masataka Mizukoshi, Taisuke Iwai, Tomoji Nakamura
  • Patent number: 7534710
    Abstract: The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts. Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter-well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Yasunao Katayama, Dennis M. Newns, Chang C. Tsuei
  • Patent number: 7498084
    Abstract: A functional device includes a pair of electrodes 1 and 4 and a macromolecular structure including a hole-conducting layer 5 and an electron-conducting layer 2. The macromolecular structure includes a first hyperbranched macromolecule and a second hyperbranched macromolecule, at least one of the first hyperbranched macromolecule and the second hyperbranched macromolecule has a hole conductivity or an electron conductivity, one of the hole-conducting layer and the electron-conducting layer includes one of the first hyperbranched macromolecule and the second hyperbranched macromolecule, and the macromolecular structure has a self-assembled structure formed by a non-covalent interaction via the first hyperbranched macromolecule or the second hyperbranched macromolecule in at least one of the hole-conducting layer, the electron-conducting layer and the interface between the hole-conducting layer and the electron-conducting layer.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: March 3, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Motohiro Yamahara, Masanobu Mizusaki
  • Patent number: 7436033
    Abstract: A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region. The effects of the gate voltage on electrons passing through the channel can be maximized, and a variation gain of current supplied between the source and drain electrodes relative to the gate voltage can be greatly increased. Thus, a molecular electronic circuit having high functionality and reliability can be obtained.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: October 14, 2008
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chan Woo Park, Sung Yool Choi, Han Young Yu, Ung Hwan Pi
  • Publication number: 20080116439
    Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.
    Type: Application
    Filed: November 8, 2007
    Publication date: May 22, 2008
    Inventors: Valery M. Dubin, Swaminathan Sivakumar, Andrew A. Berlin, Mark Bohr
  • Patent number: 7335526
    Abstract: A ChemFET Sensing system is Described.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: February 26, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kevin F Peters, Xiaofeng Yang
  • Patent number: 7109072
    Abstract: The silicon wires formed around metal particles by crystal growth have the problem of metal pollution. For its solution, in the present invention, a silicon bridge is formed through standard silicon processes such as the lithography and the wet etching using hydrofluoric acid performed to an SOI substrate. Thereafter, a thermal oxide film is desirably formed at a high temperature to form a high-quality gate insulating film. It is also desirable to form a coaxial gate electrode. Then, after burying the bridge sections of the silicon bridge in a resist film, the silicon on the bridge girders is removed, and thereafter, the silicon wires buried in the resist film are collected. In this manner, the silicon wires can be collected without dispersing into the hydrofluoric acid solution. Then, a transistor using the silicon wires as a channel is formed.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: September 19, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Saito, Tadashi Arai, Seong-Kee Park, Toshiyuki Mine
  • Patent number: 7105874
    Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: September 12, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-doo Chae, Chung-woo Kim, Ju-hyung Kim