In A Transistor Or 3-terminal Device Patents (Class 977/936)
  • Patent number: 9029836
    Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Jung-Ung Park, SungWoo Nam, Charles M. Lieber
  • Publication number: 20150053897
    Abstract: The present invention relates to a process for preparing nanoparticles of antimonides of metal element(s) in the form of a colloidal solution, using antimony trihydride (SbH3) as a source of antimony.
    Type: Application
    Filed: February 22, 2013
    Publication date: February 26, 2015
    Inventors: Axel Maurice, Bérangère Hyot, Peter Reiss
  • Patent number: 8946022
    Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, James K Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
  • Patent number: 8884345
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Patent number: 8877538
    Abstract: The present disclosure relates to a pressure sensor having a nanostructure and a method for manufacturing the same. More particularly, it relates to a pressure sensor having a nanostructure attached on the surface of the pressure sensor and thus having improved sensor response time and sensitivity and a method for manufacturing the same. The pressure sensor according to the present disclosure having a nanostructure includes: a substrate; a source electrode and a drain electrode arranged on the substrate with a predetermined spacing; a flexible sensor layer disposed on the source electrode and the drain electrode; and a nanostructure attached on the surface of the flexible sensor layer and having nanosized wrinkles.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Jin Seok Kim, Jun-Kyo Francis Suh, Sung Chul Kang, Jeong Hoon Lee
  • Publication number: 20140252495
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Application
    Filed: February 10, 2014
    Publication date: September 11, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI
  • Patent number: 8803229
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc
    Inventor: Leonard Forbes
  • Publication number: 20140158946
    Abstract: A semiconductor composition includes a semiconducting polymer containing a diketopyrrolopyrrole (DKPP) moiety and carbon nanotubes dispersed into the semiconducting polymer. An electronic device contains a semiconductor layer including a semiconductor composition having a semiconducting polymer including a diketopyrrolopyrrole (DKPP) moiety and carbon nanotubes dispersed into the semiconducting polymer. A semiconductor composition contains a semiconducting polymer including a diketopyrrolopyrrole (DKPP) moiety, a solvent selected from the group consisting of tetrachloroethane, dichlorobenzene, chlorobenzene, chlorotoluene, and a mixture thereof, and a carbon nanotube.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: XEROX CORPORATION
    Inventors: Yiliang WU, Anthony James WIGGLESWORTH, Ping LIU
  • Publication number: 20140158990
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Publication number: 20140103299
    Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Inventor: ALEXANDER KASTALSKY
  • Patent number: 8680603
    Abstract: A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Patent number: 8664091
    Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8642410
    Abstract: A catalyst film (2) is formed over a substrate (1). A graphene (3) is grown on the catalyst film (2). A gap through which a lower surface of the catalyst film (2) is exposed is formed. The catalyst film (2) is removed through the gap.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: February 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Kenjiro Hayashi, Shintaro Sato
  • Patent number: 8575665
    Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
  • Patent number: 8563966
    Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Khalifa University of Science, Technology & Research (KUSTAR)
    Inventor: Moh'd Rezeq
  • Patent number: 8557622
    Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: October 15, 2013
    Assignee: STC.UNM
    Inventors: Seung Chang Lee, Steven R. J. Brueck
  • Patent number: 8558311
    Abstract: A dielectric material is disclosed comprising a plurality of substantially longitudinally oriented wires which are coupled together, wherein each of the wires includes a conductive core comprising a first material and one or more insulating shell layers comprising a compositionally different second material disposed about the core. In one embodiment, a dielectric layer is disclosed comprising a substrate comprising an insulating material having a plurality of nanoscale pores defined therein having a pore diameter less than about 100 nm, and a conductive material disposed within the nanoscale pores.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: October 15, 2013
    Assignee: Nanosys, Inc.
    Inventors: Robert S. Dubrow, Jeffrey Miller, David P. Stumbo
  • Patent number: 8546246
    Abstract: Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Publication number: 20130228364
    Abstract: A method for positioning carbon nanotubes on a substrate, the substrate including a first electrode and a second electrode thereon, the second electrode being positioned oppositely from the first electrode; the method includes: applying a first AC voltage across the first and second electrodes; providing a first resistance in series with the first AC voltage; and introducing a solution including at least one carbon nanotube; wherein, when the first AC voltage is applied through the first resistance across the first and second electrodes, the at least one carbon nanotube attaches to the first and second electrodes. Another aspect of the invention includes providing a metallic area between the first and second electrodes.
    Type: Application
    Filed: August 26, 2008
    Publication date: September 5, 2013
    Applicant: The Trustees of Columbia University In The City Of New York
    Inventors: Sarbajit Banerjee, Irving P. Herman
  • Patent number: 8509584
    Abstract: A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals a which the SPWs may be detected. A wave guiding structure such as a 2 DEG EF facilitates propagation of the SPW within the structure so as to scatter/steer the SPW in a direction different from a pre-scattering direction. A bias SPW is excited by an application of a control SPW with a momentum vector at an angle to the bias SPW and a control current with a wavevector which scatters the bias SPW in the direction of at least one output SPW, towards a drain terminal. The NFL device is rendered with device speed as a function of SPW propagation velocity.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: August 13, 2013
    Inventor: Hector J. De Los Santos
  • Patent number: 8497499
    Abstract: A gated electrical device includes a non-conductive substrate and a graphene structure disposed on the non-conductive substrate. A metal gate is disposed directly on a portion of the graphene structure. The metal gate includes a first metal that has a high contact resistance with graphene. Two electrical contacts are each placed on the graphene structure so that the metal gate is disposed between the two electrical contacts. In a method of making a gated electrical device, a graphene structure is placed onto a non-conductive substrate. A metal gate is deposited directly on a portion of the graphene structure. Two electrical contacts are deposited on the graphene structure so that the metal gate is disposed between the two electrical contacts.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: July 30, 2013
    Assignee: Georgia Tech Research Corporation
    Inventors: Dragomir Davidovic, Walter A. de Heer, Christopher E. Malec
  • Publication number: 20130168641
    Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Inventor: Moh'd Rezeq
  • Patent number: 8455311
    Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventor: Paul M. Solomon
  • Patent number: 8450143
    Abstract: A method of fabricating a circuit includes chemically bonding a coating to a plurality of nanoparticles. The nanoparticles are dispersed in a medium comprising organic molecules. An organic semiconductor channel is formed that comprises the medium. A plurality of electrodes is formed over the substrate. The electrodes are located to function as two of a gate electrode, a drain electrode, and a source electrode of a field-effect transistor.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 28, 2013
    Assignee: Alcatel Lucent
    Inventors: Oleksandr Sydorenko, Subramanian Vaidyanathan
  • Patent number: 8445348
    Abstract: The present invention discloses a manufacturing method of a semiconductor component with a nanowire channel. The method comprises the following steps. The step of forming a stack structure on a substrate is performed. A semiconductor layer is formed on the substrate and the stack structure and further filled into the fillister. The semiconductor layer is patterned to form a source area and a drain area, and the channel region is located between the source area and the drain area. The semiconductor layer located outside the source area, the drain area and the fillister will be removed. And then, the stack structure is then removed. Therefore, the semiconductor layer filled inside the fillister will be exposed to be as a channel. A gate oxide layer is formed to cover the channel, and a gate layer is then formed on the gate oxide layer.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: May 21, 2013
    Assignee: National Chiao Tung University
    Inventors: Po-Yi Kuo, Tien-Sheng Chao, Yi-Hsien Lu
  • Patent number: 8390705
    Abstract: A photodiode includes a first electrode, a second electrode, and a nanowire comprising a semiconductor core and a semiconductor shell. The nanowire has a first end and a second end, the first end being in electrical contact with the first electrode and the second end being in contact with the second electrode.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 5, 2013
    Assignee: Hewlett-Packard Develoment Company, L.P.
    Inventors: Alexandre M. Bratkovski, Vilatcheslav V. Osipov
  • Patent number: 8383479
    Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: February 26, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, James K. Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
  • Patent number: 8361853
    Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Christos D. Dimitrakopoulos, Alfred Grill, Robert L. Wisnieff
  • Patent number: 8361907
    Abstract: A method for forming a nanowire field effect transistor (FET) device includes depositing a first semiconductor layer on a substrate wherein a surface of the semiconductor layer is parallel to {110} crystalline planes of the semiconductor layer, epitaxially depositing a second semiconductor layer on the first semiconductor layer, etching the first semiconductor layer and the second semiconductor layer to define a nanowire channel portion that connects a source region pad to a drain region pad, the nanowire channel portion having sidewalls that are parallel to {100} crystalline planes, and the source region pad and the drain region pad having sidewalls that are parallel to {110} crystalline planes, and performing an anisotropic etch that removes primarily material from {100} crystalline planes of the first semiconductor layer such that the nanowire channel portion is suspended by the source region pad and the drain region pad.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Publication number: 20130009133
    Abstract: A transistor structure is provided which includes a graphene layer located on an insulating layer, a first metal portion overlying a portion of the graphene layer, a second metal portion contacting and overhanging the first metal portion, a first electrode contacting a portion of the graphene layer and laterally offset from a first sidewall of the first metal portion by a lateral spacing, and a second electrode contacting another portion of the graphene layer and laterally offset from a second sidewall of the first metal portion by the lateral spacing.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Phaedon Avouris, Damon B. Farmer, Yu-Ming Lin, Yu Zhu
  • Patent number: 8344357
    Abstract: A 3-terminal electronic device includes: a control electrode; a first electrode and a second electrode; and an active layer that is provided between the first electrode and the second electrode and is provided to be opposed to the control electrode via an insulating layer. The active layer includes a collection of nanosheets. When it is assumed that the nanosheets have an average size LS and the first electrode and the second electrode have an interval D therebetween, LS/D?10 is satisfied.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: January 1, 2013
    Assignee: Sony Corporation
    Inventor: Toshiyuki Kobayashi
  • Patent number: 8299520
    Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
  • Publication number: 20120261167
    Abstract: Transparent electrodes, devices incorporating such electrodes, and associated methods are provided. In one aspect, for example, a method for fabricating a transparent electrode can include providing a carbon-insoluble support substrate, forming a carbon-soluble layer on the support substrate, and applying a carbon source to the carbon-soluble layer to form a plurality of graphene layers on the carbon-soluble layer. In another aspect, the method can further include providing a transparent substrate having an adhesive surface, applying the adhesive surface to the plurality of graphene layers such that the transparent substrate is adhered thereto, and removing the carbon-soluble layer and the support substrate from the plurality of graphene layers.
    Type: Application
    Filed: March 19, 2012
    Publication date: October 18, 2012
    Inventor: Chien-Min Sung
  • Publication number: 20120219702
    Abstract: A film can be patterned with a nanomaterial. Such patterning can, in various embodiments, be performed by applying a uniform mixture of a solute in a solvent to a surface of the film to form a coating of a soluble material on the surface of the film in a pre-defined pattern that defines coated parts of the film and uncoated parts of the film, depositing an aqueous dispersion, including the nanomaterial and a surfactant, on the defined coated and uncoated parts of the film, washing the film to remove the coating of the soluble material and the nanomaterial from the defined coated parts of the film, but not removing the nanomaterial from the defined uncoated parts of the film, along with removing the surfactant from the defined coated and uncoated parts of the film, and leaving a pattern of the nanomaterial on the defined uncoated parts of the film.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 30, 2012
    Inventors: Graeme Scott, Lorraine Byrne, Richard Coull, Vittorio Scardaci
  • Patent number: 8236626
    Abstract: Disclosed is a method for making graphene nanoribbons (GNRs) by controlled unzipping of structures such as carbon nanotubes (CNTs) by etching (e.g., argon plasma etching) of nanotubes partly embedded in a polymer film. The GNRs have smooth edges and a narrow width distribution (2-20 nm). Raman spectroscopy and electrical transport measurements reveal the high quality of the GNRs. Such a method of unzipping CNTs with well-defined structures in an array will allow the production of GNRs with controlled widths, edge structures, placement and alignment in a scalable fashion for device integration. GNRs may be formed from nanostructures in a controlled array to form arrays of parallel or overlapping structures. Also disclosed is a method in which the CNTs are in a predetermined pattern that is carried over and transferred to a substrate for forming into a semiconductor device.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: August 7, 2012
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Hongie Dai, Liying Jiao
  • Patent number: 8236682
    Abstract: Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The interlayer insulating layer is patterned to form an opening partially exposing the conductive pattern. An oxide layer is formed on substantially the entire surface of the substrate on which the opening is formed. A reduction process is performed to reduce the oxide layer. Here, the oxide layer on a bottom region of the opening is reduced to a catalyst layer, and the oxide layer on a region other than the bottom region of the opening is reduced to a non-catalyst layer. A nano material is grown from the catalyst layer, so that a contact plug is formed in the opening.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Rae Byun, Suk-Ho Joo, Min-Joon Park
  • Patent number: 8232165
    Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Lidija Sekaric
  • Patent number: 8232561
    Abstract: Embodiments of the invention relate to vertical field effect transistor that is a light emitting transistor. The light emitting transistor incorporates a gate electrode for providing a gate field, a first electrode comprising a dilute nanotube network for injecting a charge, a second electrode for injecting a complementary charge, and an electroluminescent semiconductor layer disposed intermediate the nanotube network and the electron injecting layer. The charge injection is modulated by the gate field. The holes and electrons, combine to form photons, thereby causing the electroluminescent semiconductor layer to emit visible light. In other embodiments of the invention a vertical field effect transistor that employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 31, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Andrew Gabriel Rinzler, Bo Liu, Mitchell Austin McCarthy, John Robert Reynolds, Franky So
  • Publication number: 20120181505
    Abstract: Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 19, 2012
    Applicant: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8222704
    Abstract: An electrical device includes a substrate; first and second active areas; first and second word lines disposed in a first plane; first and second bit lines in a second plane and in electrical communication with first and second active areas; and a reference line disposed in a third plane. A nanotube element disposed in a fourth plane is in electrical communication with first and second active areas and the reference line via electrical connections at a first surface of the nanotube element. The nanotube element includes first and second regions having resistance states that are independently adjustable in response to electrical stimuli, wherein the first and second regions nonvolatilely retain the resistance states. Arrays of such electrical devices can be formed as nonvolatile memory devices. Methods for fabricating such devices are also disclosed.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: July 17, 2012
    Assignee: Nantero, Inc.
    Inventors: H. Montgomery Manning, Thomas Rueckes, Claude L. Bertin
  • Publication number: 20120161212
    Abstract: A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.
    Type: Application
    Filed: February 27, 2012
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy Cohen, Christos D. Dimitrakopoulos, Alfred Grill
  • Publication number: 20120138905
    Abstract: Provided are a flexible organic memory device and a method of manufacturing the same. The flexible organic memory device comprises a flexible substrate. A control gate electrode is disposed on the flexible substrate. A blocking organic insulating layer is disposed on the control gate electrode. A charge trapping layer is disposed on the blocking organic insulating layer, and includes a plurality of nanoparticles. A tunneling organic insulating layer is disposed on the charge trapping layer. An organic semiconductor layer is disposed on the tunneling organic insulating layer.
    Type: Application
    Filed: June 20, 2011
    Publication date: June 7, 2012
    Applicant: Kookmin University Industry Academy Cooperation Foundation
    Inventors: Jang-Sik LEE, Soo-Jin Kim
  • Publication number: 20120104325
    Abstract: Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a solution of the same, a method for making the same from a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, imaging devices, phase change layers, and sensor devices.
    Type: Application
    Filed: April 23, 2010
    Publication date: May 3, 2012
    Applicant: THE UNIVERSITY OF CHICAGO
    Inventors: Dmitri V. Talapin, Maksym V. Kovalenko, Jong-Soo Lee, Chengyang Jiang
  • Patent number: 8153482
    Abstract: A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: April 10, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Mark Albert Crowder
  • Patent number: 8143703
    Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: March 27, 2012
    Assignee: Nanosys, Inc.
    Inventors: David L. Heald, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
  • Patent number: 8143658
    Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: March 27, 2012
    Assignee: QuNano AB
    Inventors: Lars Samuelson, Claes Thelander
  • Publication number: 20120056278
    Abstract: A manufacturing method for contacts for a semiconductor device and a semiconductor device having said contacts, said method forms contact structures whose lower part consists of a plurality of contact holes and whose upper part consists of a trench contact, said contact holes having relatively smaller diameters, and the trench contacts having relatively larger contact areas. Thus contact holes with smaller diameters and trench contacts having larger contact areas can be easily connected to the metal layer above them, thereby improving the electrical conductivity of the contacts and improving the overall performances of the device.
    Type: Application
    Filed: April 19, 2011
    Publication date: March 8, 2012
    Inventors: Huical Zhong, Qingqing Liang
  • Patent number: 8130569
    Abstract: A device for storing data using nanoparticle shuttle memory having a nanotube. The nanotube has a first end and a second end. A first electrode is electrically connected to the first end of the nanotube. A second electrode is electrically connected to the second end of the nanotube. The nanotube has an enclosed nanoparticle shuttle. A switched voltage source is electrically connected to the first electrode and the second electrode, whereby a voltage may be controllably applied across the nanotube. A resistance meter is also connected to the first electrode and the second electrode, whereby the electrical resistance across the nanotube can be determined.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 6, 2012
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventor: Alex Karlwalter Zettl
  • Publication number: 20120049890
    Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.
    Type: Application
    Filed: August 23, 2011
    Publication date: March 1, 2012
    Inventors: Ali Keshavarzi, Juanita Kurtlin, Vivek De
  • Patent number: 8120015
    Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: February 21, 2012
    Assignees: Samsung Electronics Co., Ltd., Korea University Industrial and Academic Collaboration Foundation
    Inventors: Yun-Kwon Park, Sung-Woo Hwang, Jea-Shik Shin, Byeoung-Ju Ha, Jae-Sung Rieh, In-Sang Song, Yong-Kyu Kim, Byeong-Kwon Ju, Hee-Tae Kim