Abstract: A magnetic field sensor incorporates a plurality of magnetic stripes spaced apart on the surface of a substrate such that the stray magnetic fields at the ends of the magnetic stripes are magnetostatically coupled and the magnetic stripes are magnetized respectively in alternating directions, nonmagnetic conductive material positioned in the spaces between the magnetic stripes and electrodes for passing current crosswise through the plurality of magnetic stripes to detect a change in resistance by the giant magnetoresistive effect (MGR). The invention overcomes the problem of detecting low magnetic fields since the magnetic fields required to saturate magnetic stripes depends on the magnetostatic coupling which in turn can be controlled by the geometry and position of the magnetic stripes in the sensor.

Abstract: A method for fabricating an object to attenuate thermal sensation when handling the object at non-body temperature, and an object fabricated in accord with the method. There is first provided a substrate which has a first surface subject to handling. There is then formed upon the first surface of the substrate a coating. The coating has an optimal density, an optimal thermal conductivity and an optimal thickness such that when the substrate having the coating formed thereupon is equilibrated at a non-body temperature differing from a body temperature and the coating is subsequently contacted with a body at the body temperature during handling, the temperature of the surface of the coating at a contact point of the body with the coating changes precipitously to a temperature near the body temperature and subsequently returns towards the non-body temperature at a rate which permits handling of the coating at the location of the first surface of the substrate by the body with attenuated thermal sensation.

Abstract: A method for fabricating an object to attenuate thermal sensation when handling the object at non-body temperature, and an object fabricated in accord with the method. There is first provided a substrate which has a first surface subject to handling. There is then formed upon the first surface of the substrate a coating. The coating has an optimal density, an optimal thermal conductivity and an optimal thickness such that when the substrate having the coating formed thereupon is equilibrated at a non-body temperature differing from a body temperature and the coating is subsequently contacted with a body at the body temperature during handling, the temperature of the surface of the coating at a contact point of the body with the coating changes precipitously to a temperature near the body temperature and subsequently returns towards the non-body temperature at a rate which permits handling of the coating at the location of the first surface of the substrate by the body with attenuated thermal sensation.

Abstract: Within a method for forming a metal-silicon layer there is first provided a reactor chamber. There is then positioned within the reactor chamber a substrate spaced from a metal source target. There is also provided within the reactor chamber a minimum of a sputter material and a reactive silicon material. There is then sputtered the metal source target positioned within the reactor chamber with the sputter material provided within the reactor chamber in the presence of the reactive silicon material provided within the reactor chamber to form a metal-silicon layer over the substrate. The method is particularly useful for forming metal silicate layers, metal silicon nitride layers and metal silicon oxynitride layers within microelectronic fabrications. An alternative method employs: (1) a silicon source target rather than a metal source target; and (2) a reactive metal material rather than a reactive silicon material.

Abstract: A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regions formed therein upon which is formed a low dielectric constant dielectric layer. There is then formed over the substrate a silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first subtractive etching environment the pattern into the hard mask layer. There is then subtractively etched employing the patterned hard mask layer and a second etching environment the pattern into the low dielectric constant dielectric layer, simultaneously stripping the photoresist etch mask layer.

Abstract: Within: (1) a method for purifying a metal oxide layer; and (2) a method for forming with enhanced purity a metal oxide layer, there is employed an irradiation of either: (1) a metal oxide layer; or (2) a substrate in the presence of at least one of an oxidant and a metal source material, such as to either: (1) reduce a concentration of a contaminant material within a metal oxide base material from which is formed a metal oxide layer; or (2) inhibit in a first instance formation of a contaminant material within a metal oxide layer. The metal oxide layer having incorporated therein the reduced concentration of contaminant material is particularly useful as a capacitive dielectric layer within a capacitive device within a microelectronic fabrication.

Abstract: A method for fabricating a soft adjacent layer (SAL) magnetoresistive (MR) sensor element and several soft adjacent layer (SAL) magnetoresistive (MR) sensor elements which may be fabricated employing the method. There is first provided a substrate. There is formed over the substrate a dielectric layer, where the dielectric layer has a first surface of the dielectric layer and a second surface of the dielectric layer opposite the first surface of the dielectric layer. There is also formed over the substrate a magnetoresistive (MR) layer contacting the first surface of the dielectric layer. There is also formed over the substrate a soft adjacent layer (SAL), where the soft adjacent layer (SAL) has a first surface of the soft adjacent layer (SAL) and a second surface of the soft adjacent layer (SAL). The first surface of the soft adjacent layer (SAL) contacts the second surface of the dielectric layer.

Abstract: A method comprises the step of providing a read-write element on a wafer including at least one magnetoresistive stripe, providing a shared pole layer above the magnetoresistive stripe, and planarizing the shared pole layer. Thereafter, a top pole layer is formed above the shared pole layer. Together, the shared and top pole layers form the write element. Because the shared pole layer is planarized, the gap portion of the write element between the shared and top pole layers is flat. Because of this, improved recording density can be achieved.

Abstract: A method for electrically testing an electrical circuit formed upon a substrate, and an apparatus employed within the method for electrically testing the electrical circuit formed upon the substrate. To practice the method, there is first provided a substrate having an electrical circuit formed thereupon. The substrate also has a conductor contact formed thereupon accessing the electrical circuit. The substrate is positioned within an electrical test apparatus, where the electrical test apparatus has a conductive probe tip fixed to the electrical test apparatus. The conductive probe tip is positioned in the proximity of but not in contact with the conductor contact. The conductive probe tip is then repositioned with respect to the substrate such that the conductive probe tip contacts the conductor contact while simultaneously purging the surface of the conductor contact with a purge gas stream.

Abstract: A method for forming within a deep ultraviolet (DUV) sensitive photosensitive layer formed upon a substrate employed within a microelectronics fabrication a pattern with attenuated defects and improved strippability. There is provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a photosensitive layer formed of an organic polymer resin plus additives which is sensitive to deep ultraviolet (DUV) irradiation. There is then formed within the photosensitive layer a patterned latent image by selective irradiation with a deep ultraviolet (DUV) source. There is then developed the latent image by successive treatment of the photosensitive layer to a first developer agent at a first concentration and a second developer agent at a second concentration, interspersed with aqueous solvent rinses, to form a patterned photoresist layer with attenuated residues.

Abstract: A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer.

Abstract: A method for forming integrated circuit device structures upon active semiconductor regions of a semiconductor substrate. The active semiconductor regions are defined by Field OXide (FOX) isolation regions which are formed through a Polysilicon Buffered LOCal Oxidation of Silicon (PBLOCOS) oxidation mask structure. The PBLOCOS oxidation mask structure includes a blanket pad oxide layer which resides upon the semiconductor substrate, a blanket polysilicon buffer layer which resides upon the blanket pad oxide layer and a patterned silicon nitride layer which resides upon the blanket polysilicon buffer layer. Portions of the blanket polysilicon buffer layer and the blanket pad oxide layer exposed through the patterned silicon nitride layer are completely consumed to leave remaining the patterned silicon nitride layer, a patterned polysilicon buffer layer and a patterned pad oxide layer upon the active regions of the semiconductor substrate which are separated by the FOX isolation regions.

Abstract: A method for forming within an integrated circuit a high areal capacitance planar capacitor, and the high areal capacitance planar capacitor which results from the method. There is first formed upon a semiconductor substrate a first planar capacitor electrode. The first planar capacitor electrode has a first planar capacitor dielectric layer formed thereupon, and the first planar capacitor dielectric layer has a second planar capacitor electrode formed thereupon. Formed then upon the semiconductor substrate is a Pre-Metal Dielectric (PMD) layer which is planarized until the surface of the second planar capacitor electrode is fully exposed. There is formed upon the second planar capacitor electrode a second planar capacitor dielectric layer. Finally, there is formed upon the second planar capacitor dielectric layer a third planar capacitor electrode.

Abstract: Within a method for forming a magnetoresistive (MR) sensor element there is first provided a substrate. There is then formed over the substrate a first magnetoresistive (MR) layer having formed contacting the first magnetoresistive (MR) layer a magnetically biased first magnetic bias layer biased in a first magnetic bias direction with a first magnetic bias field strength. There is also formed separated from the first magnetoresistive (MR) layer by a spacer layer a second magnetoresistive (MR) layer having formed contacting the second magnetoresistive (MR) layer a magnetically un-biased second magnetic bias layer.

Abstract: A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a dielectric passivating layer with attenuated delamination and improved adhesion to subsequent passivating and encapsulating materials. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a patterned microelectronics layer. There is then formed over the substrate a silicon containing dielectric layer employing high density plasma chemical vapor deposition (IDP-CVD) in two steps, wherein the conditions of the HDP-CVD process are optimized during the second step to provide a final layer portion with a greater degree of surface topography. Subsequently there are formed over the substrate an additional passivation layer with attenuated delamination and an organic polymer overcoat layer with improved adhesion.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a dual damascene stacked conductor interconnection layer. There is provided a substrate employed within a microelectronics fabrication wherein a series of conductor regions comprising a microelectronics conductor layer is formed within the substrate. There is then formed over the substrate a first dielectric layer. There is then formed over the first dielectric layer an intermediate low dielectric constant dielectric layer. There is then formed over the intermediate low dielectric constant dielectric layer a second dielectric layer. There is then formed over the second dielectric layer a first patterned photoresist etch mask layer, which is a contact via hole pattern. There is then etched the pattern of the first photoresist etch mask layer through the dielectric layers, employing a first anisotropic reactive etch process. There is then stripped the first patterned photoresist etch mask layer.

Abstract: A method for modulating the phase angle of a phase shift mask employed in deep ultraviolet (DUV) photolithography. There is provided a quartz substrate within which may be formed an engraved pattern, and upon which is formed a patterned phase shift layer. The phase angle of the phase shift layer upon the quartz substrate may be incrementally increased or decreased by subtractive etching of the phase shift layer and quartz substrate of the phase shift mask in an alkaline solution at a selected temperature and concentration for a period of time.

Abstract: Within a method for forming an aperture fill layer within an aperture there is first provided a topographic substrate which has formed therein a pair of mesas which defines an aperture. There is then formed over the topographic substrate and into the aperture a blanket aperture fill layer while employing a high density plasma chemical vapor deposition (HDP-CVD) method, where the blanket aperture fill layer is formed to a thickness greater than a depth of the aperture while forming a pair of protrusions over the pair of mesas. There is then etched, while employing a sputter etch method, the blanket aperture fill layer to form an etched blanket aperture fill layer such that the pair of protrusions of the blanket aperture fill layer formed over the pair of mesas is etched more rapidly than a portion of the blanket aperture fill layer formed within the aperture.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a composite dielectric layer having etched via contact holes in which via poisoning is attenuated. There is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a patterned microelectronics layer. There is then formed upon the substrate a blanket silicon containing dielectric layer employing high density plasma chemical vapor deposition (HDP-CVD). There is then formed upon the blanket silicon containing glass dielectric layer a low dielectric constant dielectric layer over which is formed a silicon oxide dielectric cap layer to form a composite inter-level metal dielectric (IMD) layer. There is then etched through the composite IMD dielectric layer a series of via contact holes. The method of formation, surface profile and properties of the blanket silicon containing glass dielectric layer provides attenuated via poisoning after via hole etching.