Abstract: A method for forming a patterned metal layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket metal layer. There is then formed over the blanket metal layer a patterned photoresist layer. There is then etched through use of a plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the blanket metal layer to form a patterned metal layer. The patterned metal layer so formed has a metal impregnated carbonaceous polymer residue layer formed upon a sidewall of the patterned metal layer. There is then stripped from the patterned metal layer the patterned photoresist layer through use of an oxygen containing plasma while simultaneously oxidizing the metal impregnated carbonaceous polymer residue layer to form an oxidized metal impregnated polymer residue layer upon the sidewall of the patterned metal layer.

Abstract: A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed horizontally spaced over the substrate a plurality of patterned microelectronics structures. There is then formed over the substrate and the plurality of patterned microelectronics structures a microelectronics layer. The microelectronics layer has a first region of the microelectronics layer interposed between the plurality of patterned microelectronics structures and a second region of the microelectronics layer not interposed between the plurality of microelectronics structures. Finally, there is processed through a grazing angle method the microelectronics layer, where the grazing angle method processes substantially all of the second region of the microelectronics layer without substantially processing the first region of the microelectronics layer.

Abstract: A plasma etch method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a plasma reactor chamber. There is then fixed within the plasma reactor chamber a microelectronics fabrication. The microelectronics fabrication comprises: (1) a substrate employed within the microelectronics fabrication; (2) a metal layer formed over the substrate; (3) a silicon containing dielectric layer formed upon the metal layer; and (4) a patterned photoresist layer formed upon the silicon containing dielectric layer. There is then etched through use of a plasma etch method at a first plasma reactor chamber pressure while employing the patterned photoresist layer as a photoresist etch mask layer the silicon containing dielectric layer to form a patterned silicon containing dielectric layer while reaching and etching the metal layer to form an etched metal layer.

Abstract: A method for forming a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a silicon oxide layer, where the silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1. Finally, there is then annealed thermally the substrate within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the silicon oxide layer a densified silicon oxide layer. The densified silicon oxide layer formed employing the method is formed with an unexpectedly low shrinkage.

Abstract: A clamp for fixturing a substrate when forming and thermally processing upon the substrate a thermally flowable layer. The clamp comprises a backing member having a top member connected through a first mechanical means to the backing member. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The clamp also comprises a shroud connected through a second mechanical means to the backing member, where a portion of the shroud overlaps the top member. The shroud leaves exposed a second portion of the substrate which is smaller than and contained within the first portion of the substrate. The shroud is removable from the backing member while the substrate remains clamped between the backing member and the top member.

Abstract: An anti-reflective reticle and a method by which the anti-reflective reticle is formed. Formed upon a first surface of a transparent substrate is a patterned metal layer. Formed upon the first surface of the transparent substrate including the patterned metal layer is a two-layer dielectric stack. The two layer dielectric stack has a first dielectric layer which is closer to the transparent substrate and a second dielectric layer which is formed directly upon the first dielectric layer. The first dielectric layer has an index of refraction greater than the index of refraction of the transparent substrate or the second dielectric layer. The second dielectric layer has a thickness of about one-quarter the wavelength of reflected light desired to be attenuated or eliminated from the surface of the reticle.

Abstract: Within a method for forming a magnetic transducer head there is first provided a substrate having formed thereover a lower magnetic pole layer in turn having formed thereupon a gap filling layer which is substantially planar. There is then formed upon the gap filling layer a patterned upper magnetic pole tip layer which serves as an etch mask layer for forming from the gap filling layer and the lower magnetic pole layer a patterned gap filling layer and an etched lower magnetic pole layer having a lower magnetic pole tip integral thereto, while simultaneously forming an etched patterned upper magnetic pole tip layer from the patterned upper magnetic pole tip layer. There is then formed upon the etched patterned upper magnetic pole tip layer and the etched lower magnetic pole layer a backfilling insulator layer to a thickness greater than a thickness of the etched patterned upper magnetic pole tip layer plus a thickness of the patterned gap filling layer plus a thickness of the lower magnetic pole tip.

Abstract: An integrated circuit having formed therein a low contact leakage and low contact resistance integrated circuit device electrode. The integrated circuit comprises a semiconductor substrate having an isolation region formed upon the semiconductor substrate. The isolation region bounds an active region of the semiconductor substrate adjoining the isolation region. There is formed at least in part within the active region of the semiconductor substrate an integrated circuit device. The integrated circuit device has an integrated circuit device electrode formed within a portion of the active region of the semiconductor substrate bounded by the isolation region. The integrated circuit also comprises a patterned metal silicide layer aligned upon the integrated circuit device electrode.

Abstract: A method for stripping an ion implanted photoresist layer from a substrate. There is first provided a substrate. There is then formed over the substrate an ion implanted photoresist layer. There is then treated the ion implated photoresist layer with a first plasma employing a first etchant gas composition comprising a fluorine containing species to form a fluorine plasma treated ion implanted photoresist layer. Finally, there is then stripped from the substrate the fluorine plasma treated ion implanted photoresist layer with a second plasma employing a second etchant gas composition comprising an oxygen containing species without the fluorine containing species. The ion implanted photoresist layer is stripped from the substrate without plasma induced damage to the substrate.

Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket chlorine containing plasma etchable layer. There is then formed upon the blanket chlorine containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched the blanket hard mask layer to form a patterned hard mask layer while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer. There is then etched the blanket chlorine containing plasma etchable layer to form a patterned chlorine containing plasma etchable layer while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer.

Abstract: A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a material which is also susceptible to etching within a fluorine containing plasma. There is then formed upon the oxygen containing plasma etchable layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while simultaneously reaching the oxygen containing plasma etchable layer and while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching the hard mask material.

Abstract: A soft adjacent layer (SAL) magnetoresistive (MR) sensor element and a method for fabricating the soft adjacent layer (SAL) magnetoresistive (MR) sensor element. To practice the method, there is first provided a substrate. There is formed over the substrate a dielectric layer which has a first surface of the dielectric layer and a second surface of the dielectric layer opposite the first surface of the dielectric layer. The is also formed over the substrate a magnetoresistive (MR) layer in contact with the first surface of the dielectric layer. Similarly, there is also formed over the substrate a soft adjacent layer (SAL) in contact with the second surface of the dielectric layer, where the magnetoresistive (MR) layer, the soft adjacent layer (SAL) and the dielectric layer are planar and preferably at least substantially co-extensive. The invention contemplates a soft adjacent layer (SAL) magnetoresistive (MR) sensor element formed employing the method of the invention.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A non-polishing planarizing method for forming a planarized aperture fill layer within an aperture within a topographic substrate layer. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths, separated by a series of apertures. The series of mesas has formed thereupon a co-extensive series of patterned sacrificial layers. There is then formed upon the topographic substrate layer and the series of patterned sacrificial layers a blanket aperture fill layer employing a deposition and sputter method to fill the series of apertures to a planarizing thickness greater than the height of the mesas, while simultaneously forming a series of protrusions of the blanket aperture fill layer corresponding with the locations of the series of patterned sacrificial layers.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a patterned first dielectric layer which defines a via accessing a contact region formed within the substrate. The patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed upon the patterned first dielectric layer a blanket second dielectric layer which completely covers the patterned first dielectric layer and fills the via. The blanket second dielectric layer is formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer which is formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma.

Abstract: A method for forming an anti-reflective coating (ARC) layer within a fabrication and a fabrication having the anti-reflective coating (ARC) layer formed therein. To practice the method, there is first provided a substrate. There is then formed over the substrate a reflective layer. There is then formed upon the reflective layer an organic polymer anti-reflective coating (ARC) layer, where the organic polymer anti-reflective coating (ARC) layer is formed from an organic polymer anti-reflective coating (ARC) material which is not susceptible to a hydrolysis reaction. There may then be formed upon the organic polymer anti-reflective coating (ARC) layer a photoresist layer which is photoexposed and developed to form a patterned photoresist layer which may be employed as an etch mask for forming a patterned reflective layer from the reflective layer. The patterned reflective layer so formed is formed with uniform and reproducible linewidth dimension.

Abstract: A method for forming upon a patterned layer within an integrated circuit an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer having a diminished pattern sensitivity. There is first provided a semiconductor substrate. Formed upon the semiconductor substrate is a patterned layer which provides a pattern sensitivity to an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer formed upon the patterned layer. The patterned layer is also susceptible to modification with a plasma which reduces the pattern sensitivity of the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer formed upon the patterned layer. The patterned layer is treated with the plasma. Finally, the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer is formed upon the patterned layer.

Abstract: A soft adjacent layer (SAL) magnetoresistive (MR) sensor element and a method for fabricating the soft adjacent layer (SAL) magnetoresistive (MR) sensor element. To practice the method, there is first provided a substrate. There is formed over the substrate a dielectric layer which has a first surface of the dielectric layer and a second surface of the dielectric layer opposite the first surface of the dielectric layer. There is also formed over the substrate a magnetoresistive (MR) layer in contact with the first surface of the dielectric layer. Similarly, there is also formed over the substrate a soft adjacent layer (SAL) in contact with the second surface of the blanket dielectric layer, where the magnetoresistive (MR) layer, the soft adjacent layer (SAL) and the dielectric layer are planar and preferably at least substantially co-extensive. The invention contemplates the soft adjacent layer (SAL) magnetoresistive (MR) sensor element formed through the method of the invention.