Abstract: A method for fabricating a copper containing integrated circuit structure within an integrated circuit, and the copper containing integrated circuit structure formed through the method. There is first provided a substrate layer. There is then formed through a first electroless plating method a nickel containing conductor layer over the substrate layer. There is then activated the nickel containing conductor layer to form an activated nickel surface of the nickel containing conductor layer. Finally, there is then formed through a second electroless plating method a copper containing conductor layer upon the nickel containing conductor layer. Optionally, there may be formed a polysilicon layer over the substrate prior to forming the nickel containing conductor layer over the substrate, where the nickel containing conductor layer is formed upon the polysilicon layer. Optionally, there may also be formed a second nickel containing conductor layer upon the copper containing conductor layer.

Abstract: A method for forming a patterned photoresist layer within an integrated circuit. The method employs a measurement parameter and a control parameter, which when at a measurement parameter target value and a control parameter target value provide a patterned photoresist layer with a target critical dimension. There is also determined a measurement parameter correlation coefficient and a control parameter correlation coefficient, each of which correlates with the patterned photoresist layer target critical dimension. When forming the patterned photoresist layer, the measurement parameter value is measured and variations of the measurement parameter from the measurement target value are compensated through varying the control parameter from the control target value while employing the measurement parameter correlation coefficient and the control parameter correlation coefficient. Through the method a patterned photoresist layer with controlled and enhanced critical dimension uniformity is formed.

Abstract: A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) exhibiting enhanced immunity to Hot Carrier Effects (HCEs), and a method by which the MOSFET may be formed. To form the MOSFET there is first provided a semiconductor substrate having a gate dielectric layer formed thereupon. The gate dielectric layer has a gate electrode formed thereupon, where the gate dielectric layer extends beyond a pair of opposite edges of the gate electrode. Formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode is a pair of low dose ion implants. Formed upon the gate dielectric layer and contacting the pair of opposite edges of the gate electrode is a pair of conductive spacers. The pair of conductive spacers partially overlaps the pair of low dose ion implants. Finally, there is formed into the semiconductor substrate adjoining the pair of opposite edges of the gate electrode and further removed from the pair of conductive spacers a pair of source/drain electrodes.

Abstract: A method and apparatus for cleaning a spray stream nozzle employed in dispensing upon a photoexposed blanket photoresist layer formed over a semiconductor substrate a photoresist developer solution. There is first provided a spray stream nozzle having a minimum of one aperture formed therein. There is then provided through the spray stream nozzle a volume of a photoresist developer solution sufficient to develop a photoexposed blanket photoresist layer formed over a semiconductor substrate placed beneath the spray stream nozzle. Finally, there is provided then through the spray stream nozzle a volume of a solvent which is not susceptible to clogging the spray stream nozzle.

Abstract: A method for removing from a patterned silicon containing dielectric layer a patterned partially fluorinated photoresist layer employed in patterning the patterned silicon containing dielectric layer. There is first formed over a semiconductor substrate a metal contact layer having a silicon containing dielectric layer formed thereover. There is then formed upon the silicon containing dielectric layer a patterned photoresist layer. There is then formed by use of a reactive ion etch (RIE) plasma etch method employing a fluorine containing etchant a via through the silicon containing dielectric layer to form a patterned silicon containing dielectric layer reaching the metal contact layer.

Abstract: A method for forming a via through a nitrogenated silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a nitrogenated silicon oxide layer. There is then formed upon the nitrogenated silicon oxide layer a patterned photoresist layer. Finally, there is then etched the nitrogenated silicon oxide layer through a reactive ion etch (RIE) plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer to form a via through the nitrogenated silicon oxide layer. The reactive ion etch (RIE) method employs an etchant gas composition comprising: (1) a perfluorocarbon having a carbon:fluorine atomic ratio at least about 1:3; (2) oxygen; and (3) argon.

Abstract: A method for forming within a microelectronics fabrication a via through a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is then formed upon the microelectronics layer a patterned photoresist layer. There is then etched through use of the fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the microelectronics layer to form a patterned microelectronics layer having a via formed through the patterned microelectronics layer.

Abstract: A method for forming a magnetic transducer structure. There is first provided a substrate. There is then formed over the substrate a lower magnetic pole layer. There is then formed upon the lower magnetic pole layer a gap filling dielectric layer. There is then formed at least in part upon the gap filling dielectric layer a patterned positive photoresist layer employed in defining through a plating method an upper magnetic pole layer formed at least in part upon the gap filling dielectric layer. The patterned photoresist layer has a first region defining a pole tip of the upper magnetic pole layer and a second region defining a magnetic coil region of the upper magnetic pole layer. The first region of the patterned positive photoresist layer is photoexposed either before or after forming through the plating method the upper magnetic pole layer defined by the patterned positive photoresist layer.

Abstract: A method for monitoring and controlling a plasma etch method for forming a patterned layer. There is first provided a substrate having a blanket layer formed thereover, the blanket layer having a patterned photoresist layer formed thereupon. There is then etched through a plasma etch method while employing the patterned photoresist layer as a patterned photoresist etch mask layer the blanket layer to form a patterned layer. The plasma etch method is monitored through an optical emission spectroscopy (OES) method which monitors a minimum of a first plasma etchant component which relates to a chemical etching of the blanket layer and a second plasma etchant component which relates to a physical sputter etching of the blanket layer and the patterned photoresist layer.

Abstract: A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas.

Abstract: A method for filling a trench within a substrate. There is first provided a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a silicon layer. The silicon layer has an aperture formed therein where the silicon layer is formed within the trench. There is then formed upon the silicon layer and filling the aperture a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) method. Finally, the substrate is annealed thermally in an oxygen containing atmosphere to form within the trench an oxidized silicon layer from the silicon layer, where the oxidized silicon layer is contiguous with a densified gap filling silicon oxide trench fill layer simultaneously formed from the gap filling silicon oxide trench fill layer.

Abstract: A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.

Abstract: A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).

Abstract: A method for removing a metal-fluoropolymer residue from an integrated circuit structure within an integrated circuit. There is first provided an integrated circuit having formed therein a metal-fluoropolymer residue. The metal-fluoropolymer residue is formed from a first plasma etch method employing a fluorocarbon containing etchant gas composition within the presence of a conductor metal layer within the integrated circuit. The metal-fluoropolymer residue is then exposed to a second plasma etch method employing a chlorine containing etchant gas composition to form from the metal-fluoropolymer residue a chlorine containing plasma treated metal-fluoropolymer residue. Finally, the chlorine containing plasma treated metal-fluoropolymer residue is removed from the integrated circuit through a stripping method sequentially employing an aqueous acid solution followed by an organic solvent.

Abstract: A method for forming within an integrated circuit a patterned conductor layer from a blanket conductor layer through a plasma etch method, where there is simultaneously avoided plasma induced electrical discharge damage to an integrated circuit structure formed beneath the blanket conductor layer. There is first provided a substrate. There is then formed over the substrate an integrated circuit structure. There is then formed over the substrate and the integrated circuit structure a blanket conductor layer.

Abstract: A method for forming a patterned photoresist layer. There is first provided a substrate. There is then formed over the substrate a blanket photoresist layer. The blanket photoresist layer is then implanted with a first ion beam to form an ion implanted blanket photoresist layer. The first ion beam employs a first ion having a first energy and a first dose sufficient such that an ion implanted patterned photoresist layer formed from the ion implanted blanket photoresist layer will not substantially outgas when the ion implanted patterned photoresist layer is exposed to a second beam. The ion implanted blanket photoresist layer is then patterned to form the ion implanted patterned photoresist layer. The method may be employed in selective high energy beam processing of the substrate. The method is particularly suited to selective high energy ion implant processing of semiconductor substrates employed within integrated circuit microelectronics fabrications.

Abstract: A method for forming within an integrated circuit a high areal capacitance planar capacitor, and the high areal capacitance planar capacitor which results from the method. There is first formed upon a semiconductor substrate a first planar capacitor electrode. The first planar capacitor electrode has a first planar capacitor dielectric layer formed thereupon, and the first planar capacitor dielectric layer has a second planar capacitor electrode formed thereupon. Formed then upon the semiconductor substrate is a Pre-Metal Dielectric (PMD) layer which is planarized until the surface of the second planar capacitor electrode is fully exposed. There is formed upon the second planar capacitor electrode a second planar capacitor dielectric layer. Finally, there is formed upon the second planar capacitor dielectric layer a third planar capacitor electrode.

Abstract: A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.

Abstract: A magnetic head/slider construction and a magnetic data recording disk, as well as a method for fabricating the magnetic head/slider construction and the magnetic data storage disk. To practice the method, there is formed over the air bearing surface of each of a magnetic head/slider construction and a magnetic data storage disk a wear resistant carbon layer. Over each of the wear resistant carbon layers is then formed a lubricating carbon layer. The lubricating carbon layers may be formed in-situ upon the wear resistant carbon layers. The wear resistant carbon layers may be formed from nitrogenated wear resistant carbon materials having a nitrogen content of from about 15 to about 30 atomic percent and hydrogenated wear resistant carbon materials having a hydrogen content of from about 15 to about 25 atomic percent. The lubricating carbon layer is preferably formed from a hydrogenated lubricating carbon material having a hydrogen content of from about 30 to about 40 atomic percent.

Abstract: A method for forming a magnetic transducer, and a magnetic transducer formed through the method. There is first provided a substrate. There is then formed over the substrate a first magnetic pole layer. There is then formed upon the first magnetic pole layer a gap filling dielectric layer. There is then formed upon the gap filling dielectric layer a seed layer. There is then formed upon the seed layer a photoresist frame employed in a photoresist frame plating method for forming a plated second magnetic pole layer upon the seed layer, where a base of a sidewall of the photoresist frame has a taper which provides a notch within an edge of the plated second magnetic pole layer at its interface with the seed layer.