Abstract: A method for forming a metal oxide semiconductor field effect transistor (MOSFET). There is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a gate electrode. There is then implanted into the semiconductor substrate while employing the gate electrode as a mask a pair of unactivated source/drain regions at a pair of opposite edges of the gate electrode, where the gate dielectric layer, the gate electrode and the pair of unactivated source/drain regions form an unactivated metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer.

Abstract: A junction diode structure formed within an integrated circuit. The junction diode structure comprises a semiconductor substrate. The junction diode structure also comprises a dielectric layer formed over the semiconductor substrate. In addition, the junction diode structure also comprises a first polysilicon layer formed upon the dielectric layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. Finally, the junction diode structure comprises a second polysilicon layer formed at least in part overlapping and at least in part in contact with the first polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity, and where a first portion of the second polysilicon layer overlapping and in contact with a first portion of the first polysilicon layer forms a junction diode within the junction diode structure.

Abstract: A method for forming a thin film resistor. There is first provided an insulator substrate. There is then formed upon the insulator substrate a blanket thin film resistive layer. There is then removed through a non-photolithographic etching method a portion of the blanket thin film resistive layer to form upon the substrate a patterned thin film resistive layer. Finally, there is then formed through a non-photolithographic printing method upon the patterned thin film resistive layer a patterned conductor lead layer. Alternatively, the portion of the blanket thin film resistive layer may be removed to form the patterned thin film resistive layer after the patterned conductor lead layer is formed upon the blanket thin film resistive layer.

Abstract: A chemical mechanical polish (CMP) planarizing method for forming a planarized organo-functional siloxane polymer dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an organo-functional siloxane polymer dielectric layer. The organo-functional siloxane polymer dielectric layer is then partially treated with an oxygen containing plasma to form from the organo-functional siloxane polymer dielectric layer an oxygen containing plasma treated organo-functional siloxane polymer dielectric upper layer and an organo-functional siloxane polymer dielectric lower residue layer. Finally, the oxygen containing plasma treated organo-functional siloxane polymer dielectric upper layer is planarized through a chemical mechanical polish (CMP) planarizing method to form a planarized oxygen containing plasma treated organo-functional siloxane polymer dielectric upper layer.

Abstract: A double layer planar polysilicon capacitor for use within integrated circuits and a method by which that planar polysilicon capacitor is formed. Formed within a semiconductor substrate is a deep trench which is filled with a dielectric material. Formed within the dielectric material within the deep trench is a shallow trench which has a first polysilicon capacitor plate formed therein. The upper surface of the first polysilicon capacitor plate is substantially planar with the semiconductor substrate. Formed upon the first polysilicon capacitor plate is a polysilicon capacitor dielectric layer. Formed upon the polysilicon capacitor dielectric layer is a second polysilicon capacitor plate.

Abstract: A method for forming a titanium nitride layer within an integrated circuit. There is first provided a substrate. There is then formed over the substrate a virgin titanium nitride layer, where the virgin titanium nitride layer is formed through a chemical vapor deposition (CVD) method employing a tetrakis-diallylamido titanium source material without a halogen activator source material. The virgin titanium nitride layer is then annealed in a first plasma comprising nitrogen and hydrogen to form a refined titanium nitride layer. The refined titanium nitride layer is then annealed in a second plasma comprising nitrogen without hydrogen. Through the method there is formed a titanium nitride layer with superior step coverage, low resistivity and low impurities concentration.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a low dielectric constant dielectric layer, where the low dielectric constant dielectric layer is formed from a silsesquioxane spin-on-glass (SOG) dielectric material. There is then formed over the low dielectric constant dielectric layer a patterned photoresist layer. There is then etched through use of a fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the low dielectric constant dielectric layer to form a patterned low dielectric constant dielectric layer having a via formed therethrough. The fluorine containing plasma etch method employing a fluorine containing etchant gas composition which simultaneously forms a fluorocarbon polymer residue layer upon a sidewall of the via.

Abstract: A method for forming a patterned target layer within an integrated circuit. The method employs a plasma pre-treatment of a patterned photoresist layer employed in patterning a blanket focusing which in turn is employed in patterning the patterned target layer from a blanket target layer. The plasma pre-treatment employs a plasma pre-treatment composition comprising carbon tetrafluoride and argon without oxygen. After the plasma pre-treatment, the blanket focusing layer is etched with a reproducible negative etch bias in a plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon without oxygen. Through the method there may be formed patterned target layers, with enhanced uniformity, of linewidth dimension as narrow as about of 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure methods.

Abstract: A method for forming for use within an integrated circuit a narrow aperture width patterned positive photoresist layer from a blanket positive photoresist layer. There is first formed over a semiconductor substrate a reflective layer. There is then formed upon the reflective layer a blanket positive photoresist layer. There is then photoexposed through a reticle the blanket positive photoresist layer to form a photoexposed blanket positive photoresist layer. Finally, the photoexposed blanket positive photoresist layer is developed to form a narrow aperture width patterned positive photoresist layer. The narrow aperture width patterned positive photoresist layer may then be employed as a narrow aperture width patterned positive photoresist etch mask layer in patterning a narrow aperture width patterned reflective layer from the reflective layer.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures.

Abstract: A method for attenuating within a microelectronics fabrication a standing wave photoexposure of a photoresist layer formed upon a reflective layer, and a microelectronics fabrication employed within the method. To practice the method, there is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a reflective layer. There is then formed upon the reflective layer a birefringent material layer. The birefringent material layer attenuates a standing wave photoexposure of a photoresist layer subsequently formed upon the birefringent material layer, where the photoresist layer is subsequently photoexposed with an actinic photoexposure radiation beam.

Abstract: A method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon containing dielectric layer. There is then formed upon the silicon containing dielectric layer a hard mask layer, where the hard mask layer leaves exposed a portion of the silicon containing dielectric layer. There is then etched partially through a first plasma etch method the silicon containing dielectric layer to form a partially etched silicon containing dielectric layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorocarbon etchant gas which predominantly forms a fluoropolymer layer upon at least the hard mask layer. Finally, there is then etched through a second plasma etch method the partially etched silicon containing dielectric layer to form a patterned silicon containing dielectric layer.

Abstract: A method for continuously monitoring and controlling the etch rates within integrated circuits of silicon nitride insulator layers and silicon nitride insulator structures in aqueous ortho-phosphoric acid (H3PO4) solutions. To practice the method of the present invention, there is first provided an etch bath chamber containing therein an aqueous ortho-phosphoric acid (H3PO4) solution. There is provided continuously from the etch bath chamber to a hydrometer cell a sample stream of the aqueous ortho-phosphoric acid (H3PO4) solution. The sample stream of the aqueous ortho-phosphoric acid (H3PO4) solution is analyzed continuously within the hydrometer cell to provide a continuous specific gravity analysis of the sample stream of the aqueous ortho-phosphoric acid (H3PO4) solution.

Abstract: A method for optically inspecting a semiconductor substrate for defects such as oxidation induced stacking faults, and a template mask which assists in practicing the optical inspection method. There is first provided a semiconductor substrate which has a surface to be inspected for defects such as oxidation induced stacking faults. Aligned then upon the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults is a template mask. The template mask has a minimum of one aperture which leaves exposed a portion of the surface of the semiconductor substrate to be inspected for defects such as oxidation induced stacking faults. Finally, there is inspected optically the portion of the surface of the semiconductor substrate exposed through the aperture.

Abstract: A clamp for fixturing a substrate when forming and thermal processing upon the substrate a thermally flowable layer. The clamp is formed from a backing member connected to a top member through a mechanical means. The backing member and the top member are sized such that a substrate may be clamped between the backing member and the top member. A portion of the top member overlaps the substrate and leaves exposed a first portion of the substrate when the substrate is clamped between the backing member and the top member. The top member has a cross-sectional profile such that a thermally flowable layer residue formed upon the top member when a thermally flowable layer is formed upon the substrate will not flow from the top member and bridge to the thermally flowable layer when the thermally flowable layer is thermally processed.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A method for forming a patterned polysilicon layer employed within an integrated circuit structure. There is first provided a semiconductor substrate having formed thereupon a topographic substrate layer. There is then formed over the semiconductor substrate including the topographic substrate layer a polysilicon layer. There is then formed over the polysilicon layer an etch mask layer. There is then etched the polysilicon layer within a first reactive ion etch (RIE) plasma employing a first etchant gas composition which comprises a chlorine containing etchant species to form a patterned polysilicon layer and a patterned polysilicon containing layer residue. Finally, there is then over-etched the patterned polysilicon layer and the patterned polysilicon containing layer residue within a second reactive ion etch (RIE) plasma employing a second etchant gas composition which comprises an oxygen containing etchant species and a bromine containing etchant species.

Abstract: A soft adjacent layer (SAL) magnetoresistive (MR) sensor element and a method for fabricating the soft adjacent layer (SAL) magnetoresistive (MR) sensor element. To practice the method, there is first provided a substrate. There is then formed over the substrate a soft adjacent layer (SAL). There is then formed upon the soft adjacent layer (SAL) a dielectric layer. There is then formed at least in part contacting the dielectric layer a magnetoresistive (MR) layer, where the soft adjacent layer (SAL) and the dielectric layer are planar. The method contemplates the soft adjacent layer (SAL) magnetoresistive (MR) sensor element formed through the method.

Abstract: A method for forming a storage capacitor within an integrated circuit cell. There is first formed upon a semiconductor substrate an integrated circuit cell. The integrated circuit cell has formed therein a Field Effect Transistor (FET) which has an exposed source/drain electrode. The semiconductor substrate also has formed therein at least one other integrated circuit device which has at least one exposed contact electrode. There is then formed upon the semiconductor substrate a blanket conductor layer. The blanket conductor layer is then patterned to form a first portion of the blanket conductor layer and a second portion of the blanket conductor layer separate from each other. The first portion of the blanket conductor layer forms a patterned conductor layer contacting the exposed contact electrode of the other integrated circuit device.