Abstract: A method for forming a silicon oxide dielectric layer within a microelectronics fabrication. There is first provided a silicon substrate layer employed within a microelectronics fabrication. There is then formed employing the silicon substrate a thermal silicon oxide layer through thermal oxidation of the silicon substrate layer. There is then formed upon the thermal silicon oxide layer a second silicon oxide layer formed through use of a thermal chemical vapor deposition (CVD) method employing ozone as an oxidant and tetraethylorthosilicate (TEOS) as a silicon source material. The thermal chemical vapor deposition (CVD) method also employs a reactor chamber pressure of from about 40 to about 80 torr. The second silicon oxide layer is formed with an attenuated surface sensitivity of the second silicon oxide layer with respect to the thermal silicon oxide layer.

Abstract: A dual stripe magnetoresistive (DSMR) sensor element, and a method for fabricating the dual stripe magnetoresistive (DSMR) sensor element. When fabricating the dual stripe magnetoresistive (DSMR) sensor element while employing the method, there are employed two pair of patterned magnetic biasing layers formed of a single magnetic biasing material. The two pair of patterned magnetic biasing layers bias a pair of patterned magnetoresistive (MR) layers in a pair of opposite canted directions.

Abstract: A polysilicon resistor structure for use within integrated circuits and a method by which the polysilicon resistor structure may be formed. A first insulating layer which is formed from a glasseous material is formed directly upon the surface of a semiconductor substrate. A polysilicon resistor is formed in contact with the first insulating layer. A second insulating layer is formed directly upon the first insulating layer and over the polysilicon resistor. The second insulating layer is formed from a silicon oxide material deposited through a Plasma Enhanced Chemical Vapor Deposition process employing silane as the silicon source material.

Abstract: A method for forming a barrier metallization layer upon a semiconductor substrate. A semiconductor substrate is provided which has formed upon its surface a barrier metallization layer. The barrier metallization layer has formed in-situ upon its surface a silicon layer. The silicon layer has a thickness such that the contact resistance of the barrier metallization layer is not substantially increased. In a further embodiment, the barrier metallization layer and the silicon layer are sintered to form a metal silicide layer upon the surface of the barrier metallization layer.

Abstract: A method for forming a patterned photoresist layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer having a first linewidth. There is then irradiated isotropically the patterned photoresist layer with an isotropic radiation source to decompose a conformal surface layer of the patterned photoresist layer while simultaneously forming a conformal surface layer decomposed patterned photoresist layer having a second linewidth narrower than first linewidth. The conformal surface layer decomposed patterned photoresist layer may then be employed as an etch mask layer when etching a blanket microelectronics layer formed interposed between the substrate and the conformal surface layer decomposed patterned photoresist layer.

Abstract: A method for forming an image array optoelectronic microelectronic fabrication, and the image array optoelectronic microelectronic fabrication formed employing the method. There is first provided a substrate having a photoactive region formed therein. There is then formed over the substrate a patterned microlens layer which functions to focus electromagnetic radiation with respect to the photoactive region of the substrate. The patterned microlens layer is formed of a first material having a first index of refraction. Finally, there is then formed conformally upon the patterned microlens layer an encapsulant layer, where the encapsulant layer is formed of a second material having a second index of refraction no greater than, and preferably less than, the first index of refraction of the first material. The method of the present invention contemplates an image array optoelectronic microelectronic fabrication formed employing the method of the present invention.

Abstract: A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a microelectronics substrate layer employed within a microelectronics fabrication. There is then formed upon the microelectronics substrate layer a patterned microelectronics layer. There is then formed conformally over the patterned microelectronics layer a conformal silicon oxide dielectric layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing silane as a silicon source material.

Abstract: A method for attenuating within a microelectronics fabrication a standing wave photoexposure of a photoresist layer formed upon a reflective layer, and a microelectronics fabrication employed within the method. To practice the methods there is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a reflective layer. There is then formed upon the reflective layer a birefringent material layer. The birefringent material layer attenuates a standing wave photoexposure of a photoresist layer subsequently formed upon the birefringent material layer, where the photoresist layer is subsequently photoexposed with an actinic photoexposure radiation beam.

Abstract: A chemical vapor deposition (CVD) method for forming with enhanced sheet resistance uniformity tungsten silicide layers upon substrates. There is formed upon a first substrate within a chemical vapor deposition (CVD) reactor chamber a first tungsten silicide layer through a chemical vapor deposition (CVD) method. The first substrate is then removed from the chemical vapor deposition (CVD) reactor chamber. The chemical vapor deposition (CVD) reactor chamber is then cleaned with a fluorine containing plasma and subsequently purged with a mixture of silane and an inert gas. There may then be formed with enhanced sheet resistance uniformity upon a second substrate within the chemical vapor deposition (CVD) reactor chamber a second tungsten silicide layer through the chemical vapor deposition (CVD) method.

Abstract: A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a polysilicon resistor. There is then formed over the polysilicon resistor a first dielectric layer formed of a silicon nitride dielectric material deposited employing a plasma enhanced chemical vapor deposition (PECVD) method other than a high density plasma chemical vapor deposition (HDP-CVD) method. Finally, there is then formed over the first dielectric layer a second dielectric layer deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method, where first dielectric layer attenuates a decrease in resistance of the polysilicon resistor incident to forming the second dielectric layer over the first dielectric layer.

Abstract: A cleaner composition for removing from within a microelectronic fabrication a copper containing residue layer in the presence of a copper containing conductor layer, and a method for stripping from within a microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer. The cleaner composition comprises: (1) a hydroxyl amine material; (2) an ammonium fluoride material; and (3) a benzotriazole (BTA) material. The cleaner composition contemplates the method for stripping from within the microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer.

Abstract: A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a planarizable layer. The planarizable layer has a lower residual portion of the planarizable layer and an upper removable portion of the planarizable layer, where one of the lower residual portion of the planarizable layer and the upper removable portion of the planarizable layer has a colorant incorporated therein. The colorant is positioned at a location which assists in monitoring and controlling an endpoint of a chemical mechanical polish (CMP) planarizing method employed in planarizing the planarizable layer. There is then planarized through the chemical mechanical polish (CMP) planarizing method the planarizable layer while employing the colorant concentration to determine the endpoint of the chemical mechanical polish (CMP) planarizing method.

Abstract: A method for inspection which involves the complete and sequential removal of an aluminum containing metallization layer, and other metal and insulator layers, from the surface of a silicon substrate. The layers are removed through sequential chemical etch processes tailored specifically to the composition of the individual layers. Upon removal of all layers, the surface of the silicon substrate is etched in a buffered aqueous etchant solution. The surface of the silicon substrate may then be inspected with the aid of an optical microscope to determine level to which the aluminum containing metallization layer has spiked into the silicon substrate.

Abstract: A method for fabricating a soft adjacent layer (SAL) magnetoresistive (MR) sensor element and several soft adjacent layer (SAL) magnetoresistive (MR) sensor elements which may be fabricated employing the method. There is first provided a substrate. There is formed over the substrate a dielectric layer, where the dielectric layer has a first surface of the dielectric layer and a second surface of the dielectric layer opposite the first surface of the dielectric layer. There is also formed over the substrate a magnetoresistive (MR) layer contacting the first surface of the dielectric layer. There is also formed over the substrate a soft adjacent layer (SAL), where the soft adjacent layer (SAL) has a first surface of the soft adjacent layer (SAL) and a second surface of the soft adjacent layer (SAL). The first surface of the soft adjacent layer (SAL) contacts the second surface of the dielectric layer.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the anisotropically patterned first dielectric layer a patterned second dielectric layer which is formed of a thermally reflowable material. There is then reflowed thermally the patterned second dielectric layer to form a thermally reflowed patterned second dielectric layer having a uniform sidewall profile with respect to the anisotropically patterned first dielectric layer while simultaneously forming a thermal silicon oxide layer upon the Schottky diode contact region of the silicon layer.

Abstract: A method for forming a planarized trench fill layer within a trench within a substrate. There is first provided a substrate having a trench formed therein. There is then formed over the substrate and at least partially filling the trench a first trench fill layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed upon the first trench fill layer a second trench fill layer formed employing a subatmospheric pressure thermal chemical vapor deposition (SACVD) method employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material. Finally, there is then planarized by employing a chemical mechanical polish (CMP) planarizing method the second trench fill layer and the first trench fill layer to form a patterned planarized trench fill layer within the trench.

Abstract: Within a soft adjacent layer (SAL) magnetoresistive (MR) sensor element which may be employed within a magnetic head there is first employed a substrate. Formed over the substrate is a soft adjacent layer (SAL). In turn, formed upon the soft adjacent layer (SAL) is a dielectric layer. Finally, in turn, formed at least in part upon the dielectric layer is a magnetoresistive (MR) layer. Within the soft adjacent layer (SAL) magnetoresistive (MR) sensor element the soft adjacent layer (SAL) and the dielectric layer are planar. In addition, within the soft adjacent layer (SAL) magnetoresistive (MR) sensor element both an upper surface of the magnetoresistive (MR) layer and a lower interface of the magnetoresistive (MR) layer are non-planar.

Abstract: A low capacitance input/output integrated circuit and a method by which the low capacitance input/output integrated circuit is formed. Formed upon a semiconductor substrate is an input/output integrated circuit which contains a minimum of one integrated circuit device. The integrated circuit device, in turn, possesses at minimum a source elect rode and a drain electrode of the same polarity. Coincident with the source electrode and the drain electrode are normally at least one ion implant of polarity opposite to the source electrode and the drain electrode. At least a portion of the drain electrode is masked when the ion implant(s) of polarity opposite to the source electrode and the drain electrode are provided into the source electrode region and the drain electrode region of the integrated circuit device(s).

Abstract: A method for etching a silicon layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing hard mask layer, where the blanket silicon containing hard mask layer is formed from a silicon containing material chosen from the group of silicon containing materials consisting of silicon oxide materials, silicon nitride materials, silicon oxynitride materials and composites of silicon oxide materials, silicon nitride materials and silicon oxynitride materials. There is then formed upon the blanket silicon containing hard mask layer a patterned photoresist layer. There is then etched through a first plasma etch method the blanket silicon containing hard mask layer to form a patterned silicon containing hard mask layer while employing the patterned photoresist layer as a first etch mask layer.