Abstract: A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.

Abstract: A self-calibrating oscillator that increases the output frequency accuracy without using a charge pump includes an oscillation circuit, a pulse counter, a charging circuit, a reset circuit, a calibration circuit, and a timing control unit. The pulse counter counts a pulse signal having frequency f0 from the oscillation circuit based on a count start signal provided from the timing control unit, while providing an output signal to the charging circuit. The charging circuit connects a constant current source and capacitor when provided with the output signal to raise the voltage at the connection node. The calibration circuit provides the oscillation circuit with a calibration value for increasing the frequency if the voltage when the output of the output signal ends is higher than a high potential reference voltage and provides a calibration value for lowering the frequency if this voltage is lower than a low potential reference voltage.

Abstract: A flip-flop circuit includes a data input, a clock input for receiving a clock signal having active edges and inactive edges, a data output, an input circuit, a pulse generator, and a latch. The input circuit sets first and second nodes to different initial logic states in response to an inactive edge of the clock signal, and selectively changes the logic state of either the first node or the second node in response to a pulse input signal to control the state of a third node, such that the selection depends on the logic state of the data input. The pulse generator circuit enables the pulse input signal in response to an active edge of the clock signal, and disables the pulse input signal in response to detecting the change in the initial logic state of either the first node or the second node. The latch stores a data output signal for output at the data output, the data output signal depending on the logic state of the third node.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: An integrated circuit includes a functional block having a plurality of standard cells. The plurality of standard cells includes a plurality of functional standard cells and a filler standard cell. Each functional standard cell of the plurality of functional standard cells has a rectangular boundary. The filler standard cell has a rectangular boundary adjacent to at least one of the functional standard cells. The filler standard cell is selectable between a first state and a second state. The filler standard cell is non-functional in the first state. The filler standard cell has functional test structures coupled to a first metal layer in the second state. This allows for test structures helpful in analyzing functionality of circuit features such as transistors without requiring additional space on the integrated circuit.

Abstract: A lead frame has multiple regions having different wetting characteristics on its surface. For example, one region is formed to handle silver plating while another has less wetting ability. A boundary between the regions causes a wetting force difference that inhibits molten solder flow between regions during solder die bonding.

Abstract: A heat spreader (50) for a semiconductor package (100) includes a heat dissipating portion (52) having a recessed periphery (54). A thermosetting resin (58) is disposed in the recessed periphery (54). The heat spreader (50) may include a heat absorbing portion (56) coupled to the heat dissipating portion (52).

Abstract: A method and system for compensating for the effect of phase drift in a data sampling clock during data transfer between sub-systems of an electronic device. The sub-systems of the electronic device transfer data frame by frame. Each frame includes multiple data windows. Each data window includes multiple data bits. The method includes sampling each of the one or more data bits of a data window at one or more early instances, a prompt instance, and one or more late instances. Further, the method includes calculating the phase-error value of the sampled data window, based on the data sampled. Furthermore, the method includes compensating for the effect of phase drift in the data sampling clock, based on the calculated phase error value.

Abstract: A multi-threaded processor that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories is disclosed. The illustrative embodiment comprises a multi-threaded processor, which itself comprises a context controller and a plurality of hardware contexts. Each hardware context is capable of storing the current state of one thread in a form that enables the processor to quickly switch to or from the execution of that thread. To enable the processor to be capable of responding to low-latency-tolerant events quickly, each thread—and, therefore, each hardware context is prioritized—depending on the latency tolerance of the thread responding to the event.

Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.

Abstract: A method for manufacturing a high quality semiconductor device having a through via structure. A substrate is manufactured with an oxide layer including a window region in a region in which a through via is formed. The substrate is bonded with another substrate to form an SOI substrate. The SOI substrate is ground to reduce its thickness. An island region is formed in a region at which a TSV (Through Silicon Via) structure is formed. A device and a TSV are coupled by a wire. The silicon substrate at a bottom side of the SOI substrate is removed to expose the island region from the bottom. A back contact for the TSV is formed in the window region, which is formed in a buried oxide layer.

Abstract: A method and an adjustable clamp system for clamping a die assembly during wire bonding. The system includes at least one pair of opposing base walls, each of the base walls has a base clamping surface. There is at least one pair of clamping members, each one of the clamping members being movable towards a respective base clamping surface to thereby clamp a lead frame of the die assembly. A die assembly support is disposed between the pair of opposing base walls and the die assembly support and pair of opposing base walls provide a cavity. There is a position sensor coupled to a controller and there is also a drive that is controllable by the controller. The drive provides movement of the die assembly support relative to each the base clamping surface to thereby adjust a depth of the cavity.

Abstract: A method for packaging a semiconductor die or assembling a semiconductor device that includes a heat spreader begins with attaching the heat spreader to a film and dispensing a mold compound in granular form onto the film such that the mold compound at least partially covers the film and the heat spreader. The film with the attached heat spreader is placed in a first mold section. A substrate having a semiconductor die attached and electrically coupled to it are placed in a second mold section and then the first and second mold sections are mated such that the die is covered by the heat spreader. The granular mold compound is then melted so that the mold compound covers the die and sides of the heat spreader. The first and second mold sections then are separated. The film, which adheres to the substrate, is removed to expose a top surface of the heat spreader, and thus a semiconductor device is formed.

Abstract: A burn-in system (10) includes an enclosure (12) defining a burn-in chamber (14). The enclosure (12) is configured to be mounted on a burn-in board (34) over a burn-in socket (36). A heating element (16) is configured to generate heat within the burn-in chamber (14) and a temperature sensor (18) is configured to sense a temperature within the burn-in chamber (14). An opening (24) is formed in the enclosure (12) for receiving a fluid (26). A controller (20) is configured to control the heating element (16) and fluid flow into the enclosure (12) in response to the temperature sensed by the temperature sensor (18).

Abstract: A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate.

Abstract: A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample.

Abstract: Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue for storing a plurality of entries. Each entry of the snoop request queue that corresponds to a snoop request includes a snoop address and a corresponding status indicator. The corresponding status indicator indicates whether the snoop request has zero or more collapsed snoop requests having a common snoop address which have been merged to form the snoop request. The status indicator is used for debug and by fullness management logic to manage the capacity of the snoop request queue. A general collapsed status signal is generated to indicate whenever any snoop queue entry collapsing occurs.

Abstract: A clock buffer for a clock network that reduces leakage current and lowers power consumption. The clock buffer includes a first CMOS transistor, a second CMOS transistor, and a leakage current prevention circuit connected to the first and second CMOS transistors. The leakage current prevention circuit includes a first PMOS transistor, which is connected between the source of a PMOS transistor of the first CMOS transistor and a power supply line, and a second PMOS transistor, which is connected between the source of a PMOS transistor of the second CMOS transistor and the power supply line. The first and second PMOS transistors are deactivated in response to an enable signal generated when a circuit block does not require the clock signal. The first and the second PMOS transistors have predefined widths and lengths such that the addition of these transistors in series with the CMOS transistors does not increase the propagation delay of the clock buffer circuit.

Abstract: An entrapment prevention and detection device for an opening/closing mechanism detects entrapment with a simple structure and does not occupy much space. When a foreign object, such as a human body part approaches a window glass, such as an automobile window, the capacitance of a capacitive sensor increases. A control circuit compares a most recent capacitance obtained by a capacitance detection circuit with a previous value and if the most recent capacitance value is greater than the previous value, when the glass is being raised (closed), the control circuit determines that a foreign object has approached the glass and then stops or lowers (opens) the glass.

Abstract: A method of attaching a solder ball to a bonding pad includes disposing flux on the bonding pad, attaching a conductive metal ring to the pad using the flux, and placing the solder ball in the ring. A reflow operation is performed that secures the ring to the pad and melts the solder ball into and around the ring. A solder joint is formed between solder ball and the pad, with the ring secured within the ball. Use of the ring allows for higher stand-off height to be achieved with similar solder ball size, without having to use bigger ball size as in the conventional method, which causes solder ball bridging. With higher stand-off height, better board level reliability performance can be obtained.