Abstract: A receiver system, which generates a soft decision signal from a hard decision signal, includes a hard output receiver for determining a received bit to generate a hard decision signal. A hard input soft output receiver determines an estimated probability of symbol data corresponding to the received bit based on the hard decision signal and generates a soft decision signal represented by a log-likelihood ratio from the estimated probability.

Abstract: An electronic device including a shielded electronic element, and a method for manufacturing a shielding structure. An oxide film is formed on the surface of a silicon substrate having a [100] face. Part of the oxide film is removed to form a first window region. Silicon substrates are joined together to form an SOI substrate, which includes a buried mask having a second window region. Substrate thinning is then performed, and oxide films are formed on the two surfaces of the SOI substrate so that the first window region has a large area and includes the region above the buried second window region. Then, anisotropic etching is performed to form a cap that includes a step. Wire bonding for shielding is performed on the step.

Abstract: A power switch circuit includes a first switch transistor connected to a main power supply, which supplies a first voltage, a second switch transistor connected in series to the first switch transistor and to a backup power supply, which supplies a second voltage. A switch control unit controls activation and deactivation of the first and second switch transistors so that either one of a voltage corresponding to the first voltage and a voltage corresponding to the second voltage is selectively output to a connection node between the first and second transistors. The first switch transistor includes a first diode, which is formed so that a direction from the main power supply toward the connection node defines a forward direction, and a second diode, which is formed so that a direction from the connection node toward the backup power supply defines a forward direction.

Abstract: A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.

Abstract: A temperature compensated current reference circuit has a differential amplifier and a first feedback transistor with a gate coupled to the differential amplifier output. The first feedback transistor couples a supply voltage line to an inverting input of the differential amplifier. There is also a second feedback transistor with a gate coupled to the differential amplifier output, which couples the supply voltage line to a non-inverting input of the differential amplifier. A first temperature dependent conductor couples the inverting input to ground. A primary reference resistor and a second temperature dependent conductor are connected in series and couple the non-inverting input to ground. An output current control transistor has a gate and one other electrode coupled together and a third electrode coupled to the supply voltage line. A secondary reference resistor and a conductivity change sensing transistor are connected in series and couple the gate of the output current control transistor to ground.

Abstract: A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal (64), and a replica bias circuit. The replica bias circuit has a first reference current source transistor, a second reference current source transistor and a reference node corresponding to the output terminal of the charge pump core circuit. The reference node is connected to gates of the second current source transistor and the second reference current source transistor. A first input of a regulator circuit is connected to the output terminal of the charge pump core circuit. A second input of the regulator circuit is connected to the reference node of the replica bias circuit. An output of the regulator circuit (54) is connected to gates of the first current source transistor and the first reference current source transistor.

Abstract: A system and method for testing a plurality of memory blocks in a System on Chip (SOC) design uses two Test Access Ports (TAPs); a user TAP and an EDA tool TAP, to provide instructions and test data to the SOC. The system includes a glue logic block, a secured logic block and a memory testing module. The glue logic block selects the user TAP at the outset of the testing phase. The secured logic block is coupled with the user TAP and generates a TAP selection signal, which controls the selection of the EDA tool TAP. The memory testing module is used to carry out the process of testing the memory blocks when the EDA tool TAP is selected.

Abstract: A charge pump and method for starting up a charge pump are provided. The charge pump comprises a plurality of charge pump cells and a start-up control circuit. Each charge pump cell has a clock terminal for receiving a delayed clock signal, an input terminal for receiving an input voltage, and an output terminal for providing a boosted voltage in response to receiving the clock signal and the input voltage. The start-up control circuit is coupled to the clock terminals of each of the plurality of charge pump cells. The start-up control circuit is for delaying the delayed clock signal provided to each charge pump cell of the plurality of charge pump cells. Each of the charge pump cells receives the delayed clock signal having a different predetermined delay so that each of the plurality of charge pump cells are enabled in a predetermined sequence during start-up of the charge pump.

Abstract: A current drive circuit allows for a reduction in chip size and prevents an output current from decreasing. The current drive circuit has an output terminal connected to a first resistor. The first resistor is connected to a second resistor and the drain of a first transistor. The gate of the first transistor is connected to the gate of a second transistor, a grounded first current source, and the source of a third transistor. A second current source and the third transistor are connected to a power supply line. The second current source is connected to the gate of the third transistor, the drain of a fourth transistor, the drain of a fifth transistor, and a second resistor. When the voltage decreases, the on resistance of the fourth transistor increases, the fifth transistor is then connected in series to the second transistor, which increases the gate voltage of the first transistor.

Abstract: An integrated circuit for detecting a bonding defect in a multi-bonding wire. The integrated circuit includes a plurality of pads each connectable by a bonding wire to a lead terminal. Voltage supplied to the lead terminal is applied in common to the plurality of pads. A detection circuit is operably connected to the plurality of pads. The detection circuit detects breakage of the bonding wires based on potentials at the plurality of pads.

Abstract: A differential amplifier that has a current supply and a differential current to voltage converter with a positive current input node, a negative current input node and a voltage output node, has offset voltage trimming. The voltage output node provides an output voltage that is proportional to the difference in current values flowing into the positive current input node and a negative current input node. A trimming circuit has a plurality of trimming control inputs, an inverting trimming output, a non-inverting trimming output and trimming inputs coupled to the current supply. Trimming resistances couple the inverting trimming output to the non-inverting trimming output. Trimming selectors, controllable by a trim code provided to the trimming control inputs, provide for selectively connecting the current supply directly to the non-inverting trimming output while selectively connecting the current supply to the inverting trimming output through a first selected group of the trimming resistances.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: A mold (10) including a first mold part (12) and a second mold part (14) define a mold cavity (16) therebetween. A gate (18) is formed in at least one of the first and second mold parts (12) and (14) such that the gate (18) communicates with the mold cavity (16). A vent (20) having a constricted portion (22) is arranged to communicate with the mold cavity (16). A substrate (28) including a base substrate (30) and an electrically conductive pattern (32) and (34) formed on the base substrate (30) may be received in the mold (10). A solder resist layer (36) is formed on the base substrate (30) and a portion of the electrically conductive pattern (32). A plurality of grooves (38) and (40) is formed in a staggered arrangement around a periphery of a molding area (42) on the substrate (28).

Abstract: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

Abstract: An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with VG=0 in a conventional H bridge circuit.

Abstract: A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.

Abstract: An apparatus and method uses a die having at least one perimeter side with multiple pads. A structure is positioned between the at least one perimeter side and the multiple pads having multiple layers within the die. The structure functions as both a strain gauge and a crack stop. The structure arrests cracks from propagating from the at least one perimeter side to an interior of the die and provides an electrical resistance value as a function of an amount of strain existing where the structure is positioned. In another form the structure is implemented on a substrate such as a printed circuit board rather than in a semiconductor die.

Abstract: A method for measuring an on resistance in an H-bridge including first and second transistors connected to a first output terminal, third and fourth transistors connected to a second output terminal, and a measurement switch connected to the first and second output terminals. The first and third transistors are connected to a first power supply terminal. The second and fourth transistors are connected to a second power supply terminal. The method includes supplying the first transistor with measurement current during a first period, measuring a first voltage at the first power supply terminal via the third transistor using the second output terminal during the first period, measuring a second voltage at the first output terminal via the measurement switch using the second output terminal during the first period, and determining the on resistance of the first transistor based on the measurement current, first voltage, and second voltage.

Abstract: A DAC unit, connected to a current supply transistor, includes first control transistors connected in parallel to each other, with each being connected in series to the current supply transistor. The first control transistors drive currents at different current values in response to a bias voltage. The DAC unit also includes second control transistors connected in parallel to each other, with each being connected in series to the current supply transistor. Each second control transistor drives the current having the same current value as one of the first control transistors in response to the single bias voltage. The first and second control transistors driving the currents having the same current value operate in a complementary manner based on part of a digital code. The DAC unit generates an output current by selectively combining at least one of the currents driven by the first control transistors.