Abstract: A load container and stabilizer subdivides and partitions a vehicle bed such as a pickup truck, van, or utility vehicle bed for stabilizing a load from shifting during travel. An elongate container constructed of flexible fabric material panels extends between opposite sides of the vehicle bed. The flexible fabric material panels forming the elongate container subdivide or partition the vehicle bed for stabilizing a load. The load rests on the floor of the vehicle bed and is restrained from shifting by the flexible fabric material panels. Flaps are formed at the top of respective sides of the elongate container and extend over surfaces of the sidewalls of the vehicle bed. Fasteners secure the flaps and elongate container to the sidewalls at desired locations along the vehicle bed. Typically, the flaps are secured to the upper surface of shelves formed along the sidewalls. Multiple elongate containers can be deployed.

Abstract: A semiautomated machine (10) cuts a disk (60a) from the mouth side of sea urchin shells (60) for efficient extraction of gonads, the sea urchin reproductive organs, with minimal damage. The machine is capable of preserving intact the original five segmented star configuration. A conveyor (12) receives and retains sea urchins (60) with the mouth side of the sea urchin shells facing away from the conveyor. A cutter (15) is mounted over the conveyor at a cutting location (16). A relatively thin elongate cutting element (38) is spaced from the conveyor (12) and oriented generally transversely across the conveyor. An extended aligning plane (65,66) parallel to the conveyor is mounted on the opposite side of the elongate cutting element (38) from the conveyor (12) at the cutting location (16). The aligning plane (66) contacts the mouth side of the sea urchin shells and aligns and maintains orientation of the sea urchins with the mouth side of the sea urchin shells facing the aligning plane.

Abstract: A masonry heater (11) confines combustion within a core (15) of refractory material construction. The core includes a primary combustion firebox (18) with fuel access firebox door (20) and a secondary combustion chamber bakeoven (25) over the firebox (18) with a bakeoven access door (26). A tapered throat (35) provides a flue coupling from the firebox (18) to the bakeoven (25). The tapered throat (35) is constructed from a plurality of unmortared replaceable refractory bricks accessible for replacement through the bakeoven door (26). The tapered throat refractory bricks (80,86) are constructed in configurations to rest on each other and provide a structurally self supporting tapered throat structure (55) with at least two sloping sides. The core (15) is constructed with a first course (50) of shelf firebricks (52) providing shelf projections (50,52,54) for supporting the unmortared replaceable refractory bricks (80,86) of the tapered throat structure (55).

Abstract: A tool holder for holding tools includes a pair of walls extended forward from a board, a number of pairs of notches are formed in the walls for accommodating the tools. Each of the notches includes two ends, in which a shoulder is formed in one end and the other end is located closer to the board. A number of resilient members are projected forward of the board and each aligned with one pair of the notches, the resilient members project inwards of the notches for biasing the tools against the shoulders such that the tools can be stably held in place.

Abstract: A multiport valve for a water transfer system passes water, drawn by a pump, through a plurality of collectors. A programmable controller controls operation of the pump and a stepper motor which positions the multiport valve in a time series sequence according to user instructions. The multiport valve is formed with a first valve head having an intake port and multiple separate outlet ports. The respective outlet ports are connected to the respective collectors at respective collector inlets. A first rotor bears against the first valve head and forms a seal between the first rotor and first valve head. The first rotor is formed with a first coupling channel for coupling the intake port of the first valve head to different outlet ports according to the rotational position of the first rotor. The multiport valve incorporates a second valve head formed with an exhaust port and a plurality of separate inlet ports coupled to the respective plurality of collectors at respective collector outlets.

Abstract: A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC).

Abstract: New molded pulp and molded fiber structures provide interior package cushioning to protect products shipped in a package. The molded pulp fiber interior package cushioning (IPC) structure defines a cavity for receiving and holding a product to be shipped. The IPC structure incorporates a plurality of structural ribs in the form of elongate hollow ridges molded in the IPC structure and extending between different locations for reinforcing the IPC structure between the locations. The IPC structure comprises intersecting ribs extending in at least two orthogonal directions or axes.

Abstract: A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL.

Abstract: A temperature compensated ECL output driver circuit incorporates an ECL output gate (Q4,Q3) coupled between high (V.sub.CC) and low (V.sub.EE) potential power rails with output voltage swing resistors (R2, R1). The ECL output gate provides an output node (N1) at the collector node of one of the ECL output gate transistors (Q4). A first current sink (Q5,R4) is coupled between the common emitter node coupling (N3) of the ECL output gate (Q4,Q3) and low potential power rail (V.sub.EE). A compensating current source (Q11,R5) is coupled to the ECL output gate output node (N1) for generating a supplementary compensating current during operation of the ECL output driver circuit in intermediate and high temperature operating ranges. A compensating current switch (Q9,Q10) is coupled in the compensating current path and is constructed for switching off the supplementary compensating current in a specified low temperature operating range to maintain the logic high output signal V.sub.OH within specifications.

Abstract: A solar collector converts solar radiation to heat energy over a specified surface area and collects the heat energy by trickle feeding a heat transfer fluid over a trickle feed absorber surface having improved absorber surface area to volume ratio. The elements of the solar collector include a glazing first layer for receiving and passing incident solar radiation over the specified surface area and an impervious backing layer spaced from the glazing first layer. The absorber layer is sandwiched between the glazing first layer and backing layer with the glazing first layer and backing layer contacting the absorber layer on opposite sides. The absorber layer is a layer of fiber material defining capillary channels and spaces in the absorber layer between the glazing first layer and backing layer.

Abstract: A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal.

Abstract: A machine for making steel grids each consisting of a number of steel strips attached to a number of steel rods at an angle of 90.degree.. The steel strips are formed with temporarily softened spots by means of the machine. The steel rods are pushed into the temporarily softened spots by means of the machine.

Abstract: A bird feeder protector startles and removes unwanted animal intruders from a bird feeding area or bird feeding platform of a conventional bird feeder. A protector mounting base is secured to the bird feeder. A sweeper arm is provided with sufficient length to sweep across the bird feeding area. A mounting spring mounts the sweeper arm on the protector mounting base in a rest position adjacent to the bird feeding area and generally parallel with the bird feeding area. The sweeper arm is positioned to sweep across the bird feeding area upon bending the mounting spring. The mounting spring is selected with a spring constant for restoring the sweeper arm to the rest position. A line is coupled to the sweeper arm for pulling the sweeper arm at a remote viewing location and bending the mounting spring.

Abstract: A new IC wafer fabrication process provides an improved CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable for preparation of CMOS transistors in BICMOS wafers. The new gate oxide process reduces the number of process steps and thermal cycles, increases the reliability of the gate oxide layer, and substantially reduces differential stress and thermal stress related structural silicon defects in the epitaxial silicon. The process proceeds by forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer. Further steps include introducing dopant material through the EPIOX layer into the EPI layer of CMOS transistor active areas with the photoresist active strip mask in place and adjusting the threshold voltage V.sub.T of the CMOS transistors.

Abstract: An integrated circuit constructed using exposure and etching steps in an FET fabrication process incorporates electrical lead structures coupled to distributed IC components to compensate for process variation. The electrical lead structure (10,14,16,24,34is composed of an etchable conductive layer constructed in a configuration with graduated coupling widths (B,C,D,E . . . ) forming a graduated range of respective etchable dimensions arranged in an electrically coupled sequence. A primary lead (IA) is coupled at a first end to the widest coupling width (B). A plurality of secondary leads (0B,0C,0D,0E . . . ) distributed along the electrically coupled sequence of graduated coupling widths are coupled respectively to the distributed electrical component elements (P1B,P1C,P1D,P1E . . . ) (N1B,N1C,N1D,N1E . . . ) (RB,RC,RD,RE . . . ) of a distributed electrical component such as a PMOS transistor (P1) NMOS transistor (N1) or resistor (R). The graduated coupling widths (B,C,D,E . . .

Abstract: A BICMOS input buffer circuit (20) incorporates an integral CMOS passgate circuit (P2,N2) between bipolar input (Q1) and output (Q3,Q4,Q5) transistors of the input buffer circuit. Latch enable inputs (LE) receive latch enable signals for operating the input buffer circuit and internal passgate in a transparent mode for passing data signals from the input (V.sub.IN) to the output (V.sub.OUT) and in a blocking mode for blocking data signals. The internal CMOS passgate circuit (P2,N2) is coupled into the input buffer circuit (20) to control nodes of the transistor output pullup (Q4,Q5) and pulldown (Q3) for controlling the conducting states of the respective transistor output pullup and pulldown to implement the blocking and transparent modes. A third passgate transistor (P3) may also be coupled between a control node (m1) of the transistor output pullup (Q4,Q5) and the low potential power rail (GND) for positive turn off of the output pullup.

Abstract: A wafer structure and a method of fabricating and testing IC dies (10) on a wafer (12) are incorporated in a wafer fabrication process which produces IC dies having a selected sensitive AC parameter (L.sub.EFF,.beta.,R). Performance of the sensitive AC parameter generally falls within a first range of variation characteristic of the wafer fabrication process. A test structure or test pattern (TNMOS, TPMOS, TNPN, TR) is formed on substantially every die (10) of the wafer (12) for testing in a DC parametric test at the wafer level sorting stage before scribing and packaging the dies from the wafer. The test structures are constructed for generating test measurements in a DC parameter test reflecting the AC performance of the selected sensitive AC parameter. Substantially every die on the wafer is tested at the wafer level sorting stage using the test structures (TNMOS, TPMOS, TNPN, TR) in a DC parametric test. Those dies of the wafer reflecting AC performance of the selected sensitive AC parameter (L.sub.EFF, .

Abstract: An output buffer circuit (10,11) is protected by a short circuit protection circuit (12) from short circuit conditions at the output by detecting occurrence of a short circuit condition of the output (V.sub.OUT) shorted to either the high or low potential power rails (V.sub.CC, GND) and by tristating the output buffer circuit upon detecting the short circuit condition. Detection of a short circuit condition is accomplished by sensing and comparing the respective states of signals at the input (V.sub.IN) and output (V.sub.OUT) and detecting occurrence of an out of state condition between the input and output. If the out of state condition is sensed for a sensing time delay period (tC1, tC2) longer than characteristic propagation delay times (tpHL, tpLH), a short circuit sensing signal (VLO, VHI) is generated.

Abstract: A TTL to CMOS translating input buffer circuit receives TTL input data signals at an input (V.sub.IN) and delivers CMOS data signals at an output (V.sub.OUT). The input buffer circuit is provided with an expanded first stage with expanded pullup circuit (P1) and pulldown circuit (N1) having control gate nodes coupled to the input (V.sub.IN). The pullup and pulldown circuits (P1,N1) are constructed to provide dual switching thresholds at the input (V.sub.IN). A first stage output pullup and pulldown circuit (P1R,P1L,N1L) switches at a relatively lower first threshold voltage level. A pullup enhancer circuit (P1E,I3,I4) switches at a relatively higher second threshold voltage level. The pullup and pulldown circuits (P1,N1) of the expanded first stage are constructed for switching dynamic current at an output node (m1) at the relatively lower first threshold voltage level for data signal transitions between high and low potential levels at the output node (m1).