Abstract: A solar thermal collector incorporates an extended reflector surface constructed to concentrate radiation from a radiation source along a focal line. The reflector surface is oriented in a generally upward facing direction relative to the earth with the focal line above the reflector surface. A tracking system supports the extended reflector surface for double axis tracking of the sun by relative motion of the reflector surface to different tracking positions for optimizing concentrated radiation at the focal line. The tracking system is constructed to maintain the focal line of the extended reflector surface in a substantially horizontal orientation relative to the earth during tracking. An elongate absorber is positioned substantially at the focal line for absorbing and converting radiation to heat energy. An elongate absorber housing is coupled to the extended reflector surface and is constructed for positioning the elongate absorber substantially along the focal line.

Abstract: Apparatus (10) and method for solder finishing the leads of an integrated circuit package are applicable to "flat packs" or flat packages having coplanar rows of leads (84) along sides of the flat package (75). First and second tracks (22,26) are formed with elongate first and second supporting surfaces (72,74) oriented with the first and second supporting surfaces at opposite first and second downwardly depending angles (.THETA.1,.THETA.2). First and second index edges (70) are formed along the respective first and second supporting surfaces of the first and second tracks (22,26) for retaining a flat package (75) at the respective opposite first and second downwardly depending angles. Vertical first and second falling columns of molten solder are established at first and second loci of solder finishing (16a,16b) defined by solder bridge sections (66,68) with the first and second falling columns (85) located on the lower sides of the respective first and second tracks (22,26).

Abstract: A total precipitation gauge (10) incorporates a float gauge (16) extending downward to a liquid level (18) in a precipitation storage container. The float gauge (16) is formed with an elongate stillwell (20) extending into the liquid level (18), a float element (22) suspended in the stillwell (20) for rising and falling motion within the stillwell in response to the liquid level, and an elongate code bearing surface (24) coupled to the float (22). A code sensor (34) senses motion of the code bearing surface (34) for generating electrical signals (35) corresponding to motion of the float element and liquid level. The code bearing surface is a flexible coded strip (24) secured at one end to the float element (22) and at the other end to a spring loaded reel (25). The spring force of the spring loaded reel (25) is less than the weight of the float element (22) and ballast (26).

Abstract: A contact test structure and method provide accelerated testing of long term reliability of metal to silicon ohmic contacts and adjacent PN junctions on IC dies of a wafer. At least one wafer level reliability contact test structure (10) is formed on the wafer during CMOS or BICMOS wafer fabrication mask sequences without additional steps. A shallow layer (N+S/D) of semiconductor silicon material of second type carrier (N) conductivity is formed in a well (PWELL) of first type carrier (P) conductivity silicon material with a shallow PN junction (J) between the shallow layer and well. Metal to silicon first and second test contacts (TC1,TC2) of metal layer portions (M1) are formed at first and second locations on the shallow layer (N+S/D) spaced apart a selected distance. The second test contact (TC2) has a contact area between a metal layer (M1) and shallow layer (N+S/D) in the minimum size range for the fabrication process for maximizing current density through the second test contact (TC2).

Abstract: A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP).

Abstract: A skew tester (60) measures output timing skew parameters OSHL and OSLH between multiple output signals of an integrated circuit (IC) device under test (DUT) having an input and multiple outputs. A measurement signal generating circuit (15,16,18,20) generates a square wave measurement signal at a test signal frequency synchronized with a clock signal. The measurement signal generating circuit uses direct digital synthesis to provide a specified phase shift resolution. A test signal generating circuit (15,22,24) generates a square wave test signal at the test signal frequency using the same clock signal. The test signal and measurement signal are therefore synchronized in frequency. The test signal is applied to the input of a DUT (25) and a switch (30) selects one of the DUT output signals.

Abstract: A programmable and controllable timing circuit (CTC) is formed on an integrated circuit chip (IC) having a test access port (TAP) with TAP access pins including a TAP data input (TDI) pin, a TAP data output (TDO) pin, a TAP mode select (TMS) pin, and a TAP clock (TCK) pin. The test access port includes a plurality of TAP data registers (TDRs) coupled to receive data signals at the TDI pin and to shift data signals to the TDO pin. A TAP instruction register (TIR) is coupled to receive instruction codes at the TDI pin and to direct use of selected TDRs. A TAP controller is coupled to receive control signals at the TMS pin and clock signals at the TCK pin and provide control and clock signals for controlling operation of the TIR and TDRs. The TAP is provided with a controllable timing circuit design specific TAP data register (CTC/DS/TDR) constructed for receiving a coded CTC digital timing code at the TDI pin.

Abstract: An edge controlled output buffer circuit reduces the amplitude of power rail noise while maintaining high switching speed by controlled storage and release of charge at the output using new charge storage and discharge capacitor circuits coupled to the output. An output discharging storage capacitor (C1) is coupled to the high potential power rail (V.sub.CC). A first passgate circuit PSGT1 is coupled between the charge storage capacitor (C1) and the output (V.sub.OUT). A first control circuit (CTR1) is coupled to the control node (m2) of the first passgate circuit (PSGT1) for transient turn on of the first passgate circuit (PSGT1) when the output is still at high potential level during transition from high to low potential level at the output. A second passgate circuit (PSGT2) is coupled between the charge storage capacitor (C1) and the low potential power rail (GND).

Abstract: CMOS output circuit improvements control output signal rise and fall times during transition between high and low potential levels at the output (V.sub.OUT). A plurality of pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N) are coupled in parallel paths in the pulldown predriver circuit. Respective resistance values slow turn on of the output pulldown driver transistor (N1) for achieving a plurality of different fall times. A plurality of pulldown predriver switch transistors (PS1, PS2, PS3) are respectively coupled in series with the pulldown predriver resistors (R1.sub.N, R2.sub.N, R2.sub.N). The switch transistors (PS1, PS2, PS3) have respective control inputs (V.sub.S1, V.sub.S2, V.sub.S3) for selecting respective parallel paths containing the different pulldown predriver resistors (R1.sub.N, R2.sub.N, R3.sub.N). A plurality of pullup predriver resistors (R1.sub.P, R2.sub.P, R3.sub.P) are coupled in parallel paths in the pullup predriver circuit.

Abstract: In a BiCMOS TTL output buffer circuit, bipolar output pullup and pulldown transistors (Q3,Q4,Q5) source and sink current at an output (V.sub.OUT). A phase splitter transistor (Q2,N4) is coupled to the bipolar output pullup and pulldown transistors for controlling respective conducting states in response to data signals at an input (V.sub.IN) during the active bistate mode of operation. CMOS tristate transistors (P1, ,P2,P4,N2) form a tristate circuit for implementing an inactive tristate mode at the output V.sub.OUT in response to tristate enable signals at a tristate enable input (OE). In order to reduce quiescent input current (I.sub.CC) power dissipation, an input power switch CMOS transistor (NI,N4,P1A) is coupled in the input current path to the high potential power rail (V.sub.CCI). The control gate node of the input power switch CMOS transistor (N1, ,N4,P1A) is coupled to the input (V.sub.IN) to control sourcing of input current (I.sub.

Abstract: An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN).

Abstract: A full motion video telephone system combines mechanical scanning from the early era of television with modern video and digital communications technology for operation over conventional loaded bandwidth limited telephone lines. A camera pickup mechanical disk scanner causes scanning of an object in picture frames with an image resolution in the range of 30-90 scan lines per frame and full motion resolution in the range of 15-30 frames per second. A photomultiplier sensor generates an analog serial scanning signal with a bandwidth within the analog frequency range of 0-90 kHz. The synchronous motor of the mechanical scanner is synchronized with a first clock signal generated from a reference clock standard. Analog to digital conversion permits transmission by a high speed modem on the telephone lines. The receiving station is similar permitting full motion image reproduction with acceptable resolution.

Abstract: A tool for trimming edge portions of linoleum to fit against a bordering wall has leading and trailing ends and a downwardly opening throat which extends lengthwise of the tool and opens through the ends thereof. The throat is dimensioned to enable an edge portion of the thickest and stiffest linoleum to be entered in and pass through the throat and be held upwardly curved against the outer wall of the throat as the tool is advanced along the wall with spaced edge portions in engagement with the wall at its junction with the floor or a covering thereon and disposed to hold the front of the tool out of contact with the wall or a baseboard. The tool has a holder for a blade exposed in the throat in the trailing end and disposed to sever the edge portion against the outer or front wall of the throat as the tool is advanced.

Abstract: A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode.

Abstract: A turf spiking tool attachment 10 retrofits turf aerating machines 20 having reciprocating pistons 20 with the turf spiking tool attachments 10 mounted on the free ends of the pistons 20 for motor driven punching and aerification of turf. A flat base plate or punch plate 11 is secured to the free end of a piston. A plurality of spiking tines 13 project from the base plate 11. A stripper plate 12 is formed with a plurality of openings 18 in alignment with the projecting tines 13 of the base plate. The stripper plate 12 is mounted adjacent to the base plate 11 for sliding motion relative to the base plate. Guide elements 15,16 maintain the stripper plate and base plate substantially in parallel alignment. The stripper plate 12 bears against the turf. A stripper spring 17 pushes the stripper plate against the turf, holds the turf in place during retraction of the tines 13, and returns the stripper plate 12 to a starting position.

Abstract: A V.sub.OH clamp circuit reduces propagation delay time TP.sub.HL and reduces ground bounce noise in TTL output buffer circuits. First and second band gap bias generators (BG1,BG2) coupled in series provide a substantially stable clamp reference voltage level (V.sub.R) over a specified range of operating temperatures. The clamp reference voltage level (V.sub.R) is referenced to the low potential power rail (GND). Voltage drop components (D32,QC) of the Y.sub.OH clamp circuit couple the reference voltage level (V.sub.R) through the voltage drop components (D32,QC) to an internal node, namely the base node (BDAR) of the pullup Darlington configuration transistor pair (Q12A,Q12B), The V.sub.OH clamp circuit clamps the high potential level output signal (V.sub.OH) at a maximum voltage level (V.sub.OHMAX) less than the high potential level power rail (V.sub.cc), and referenced to the clamp reference voltage level (V.sub.R).

Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.

Abstract: An output buffer circuit incorporates a ground bounce blocking circuit which blocks transfer of ground bounce pulses from the output ground lead (GND,PGND) to the output (V.sub.OUT) for protecting quiet outputs tied to a common ground bus. A diode element (SD1,D1,ND1, NSC) is coupled in the sinking current path in series with the primary pulldown transistor element (N1,N1P) between the buffer circuit output (V.sub.OUT) and the ground rail (GND,PGND). The diode element is oriented for passing sinking current to the low potential ground rail and for blocking transfer of ground bounce pulses originating in the ground rail (GND,PGND) to the output. The ground rail may be bifurcated to provide a relatively noisy output ground lead (PGND) and a relatively quiet ground lead (QGND). The primary pulldown transistor element (N1P) is coupled to the relatively noisy output ground lead (PGND).

Abstract: A CMOS oscillator integrated circuit in a Pierce crystal oscillator circuit configuration operates at oscillating frequencies over a wide band frequency range. A single inverter stage (I1) is coupled between the oscillator input (OSC IN) and the oscillator output (OSC OUT). An oscillator feedback circuit coupled between the oscillator output and oscillator input incorporates an oscillator crystal (XTAL). A pullup gain network (PNET) provides a plurality of different parallel pullup gain paths between the pullup transistor (P1) of the inverter stage (I1) and the high potential power rail (V.sub.CC). The pullup gain paths have different pullup gain resistances (RP2, RP3, . . . RPN) in the respective pullup gain paths for implementing different amplifying gains (A.sub.N) by the inverter stage (I1). Digitally addressable pullup gain switches (P2, P3, . . . PN) are coupled in respective pullup gain paths for selecting different gain paths and different amplifying gains (A.sub.N).