Abstract: A synchronous counter flip flop circuit (20) incorporates a logical AND input circuit (22) having multiple inputs (24) and a first output (25) delivering a first count signal upon concurrence of count logic signals at count logic signal inputs (BIT0-BIT7) with a count enable clock signal at a count enable clock signal input (CET). A count delay circuit (30) is coupled to the first output (25) to provide a second output (32) in parallel with the first output (25) for delivering a delayed second count signal. A logical AND intermediate circuit coupling (34) having first and second inputs coupled respectively to the first and second outputs (25,32) provides a third output (35) delivering a third count signal which is a filtered intermediate terminal count signal (TC). An inverting output buffer circuit (26) provides a final inverted filtered terminal count signal (TC) at the final terminal count output (28).

Abstract: A BICMOS passgate circuit (PSGT3) (PSGT3A) for use in latches and flip-flops incorporates a bipolar output circuit (Q1,Q3) comprising a bipolar pullup transistor element (Q1) and a bipolar pulldown transistor element (Q3) coupled to the passgate output (V.sub.OUT) for transient charging and discharging of load capacitance (C.sub.L) at the passgate output (V.sub.OUT). The bipolar output circuit provides increased sinking and sourcing output drive current and .beta. amplification of sinking and sourcing drive current at the passgate output V.sub.OUT in response to data signals at the passgate intput (V'.sub.IN) in the transparent operating mode. An MOS input logic circuit coupled to the passgate input (V'.sub.IN) includes clock signal inputs (CP,CP) for implementing transparent and blocking operating modes.

Abstract: A wind speed and wind direction indicator is constructed on a center support pole or mast having a vertical scale of wind speed indicia for visually reading wind speed at a distance from the pole. A swivel head is mounted at the top of the pole for rotation to different compass directions. A rigid arm pendulum is pivotally coupled to the swivel head for pivotal motion of the pendulum to different angles with respect to the support pole. A wind drag structure such as a wind sock is coupled to the free end of the rigid arm pendulum for angular positioning in response to varying wind speed. A sliding collar is mounted on the support pole for sliding motion up and down over the scale of wind speed indicia. A line is coupled between the free end of the rigid arm and the sliding collar for sliding motion of the collar over the scale of wind speed indicia in response to varying wind speed.

Abstract: A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time.

Abstract: An anti-noise circuit dissipates parasitic tank circuit energy which causes ground unershoot and V.sub.cc overshoot in the power rails (PG,PV) of an integrated circuit device. An anti-noise circuit transistor element, either an anti-undershoot circuit transistor element (AUCT) or an anti-overshoot circuit transistor element (AOCT) incorporates selected resistance in its primary current path for providing dissipating resistance. The anti-noise circuit couples a current source (PV), the anti-noise circuit transistor element (AUCT, AOCT) with dissipating resistance, and power rail parasitic lead inductance in series in a sacrificial current path. A control circuit coupled to the control node of the anti-noise circuit transistor element (AUCT,AOCT) causes sacrificial current flow following switching of potential levels at the output for dissipating parasitic tank circuit energy. The control circuit incorporates an active pullup and pulldown passgate (RST1,ICT1,OCT1) (RST2,ICT3, OCT2) between the data input (V.

Abstract: An ECL to TTL translator circuit incorporates an ECL input gate, a TTL output gate, and a voltage amplifier transistor element circuit coupled between the ECL input gate and TTL output gate for effecting the translation. The ECL gate has differential ECL inputs for receiving ECL input signals at least at one of the ECL inputs (V.sub.IN) and differential first and second ECL output nodes (A, B). First and second emitter follower output circuits (Q7, Q3) are coupled to the respective first and second ECL output nodes (A, B). The TTL gate (12) has a TTL output (V.sub.OUT) for delivering TTL output signals corresponding to ECL input signals. The TTL gate phase splitter transistor element (Q9) controls the TTL output (V.sub.OUT). The collector node of a voltage amplifier transistor element (Q6) is coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element.

Abstract: A pin electronics test circuit applies test signals at a pin of an ECL integrated circuit (IC) device under test (DUT) and senses and measures pin signals received from a pin of the DUT. The pin electronics test circuit incorporates test signal first and second electrical paths (TL1, TL2) (TL11, TL12) with respective test connect and disconnect first and second nodes (n1)(n2). First and second termination circuits (RL1, A1)(RL2,A2), first and second DC test signal generators (A1 etc.) (A2 etc.) for forcing DC test signal voltages and currents, AC test signal generator (I.sub.HI, I.sub.LO etc.) for switching between and driving AC test signals of high and low potential levels, and pin signal sensing and measuring circuits (CR1, 8CR2) are all contained on a single pin electronics card (PEC) (54) or formed as a single unit for a pin or complementary pair of pins of the DUT.

Abstract: A new composite material of an open foam substrate and bonded micropackaged active ingredient particles is generated by foam polymerization of a prepolymer phase and an aqueous phase. The foam substrate is an open cell foam for dispensing active ingredient liquids or solids released from the particles. The particles of micropackaged active ingredient liquids or solids are formed with frangible containment walls for breaking and releasing the active ingredient in response to defined stress. The aqueous phase is a pourable and flowable slurry mixture of an aqueous liquid carrier such as water, micropackaged active ingredient particles in the range of 1%-60% by weight of the aqueous phase, and surfactant wetting agent for adjusting the surface tension of the aqueous phase to produce an open cell foam upon polymerization with the prepolymer phase. The prepolymer phase is a hydrophilic polyurethane prepolymer receptive to the aqueous phase for foam polymerization upon mixing.

Abstract: An electrical connector (10) provides a mechanical coupling and an electrical interface between circuit boards (12,14). An elastomeric electrical conductor (20) provides compressible electrical connector paths between first and second sets of electrical contact pads (28,15) coupled to the respective circuit boards. A compression mounting assembly (22) aligns and retains the elastomeric electrical conductor (20) between the sets of electrical contact pads. The elastomeric electrical conductor (20) affords relatively high frequency signal conducting paths with substantially constant impedance for example for passing test signals and pin signals without distortion between circuit boards in the test head of an IC device tester. A mechanical spring system (64,65) spring loads the compression mounting assembly (22) and provides a relatively high mechanical compliance coupling between circuit boards (12,14) to accommodate relative change of position of the boards due to misalignment or board warpage.

Abstract: TTL to CMOS level translating buffer circuits incorporate multiple stages with feedback and forward couplings between stages that eliminate static current I.sub.cct when TTL high potential level data signal is applied at the buffer circuit input. The feedback and feed forward couplings maintain and enhance signal propagation speed in the buffer circuits at the same time. TTL to CMOS translating latch circuits and flip-flop circuits similarly incorporate feedback and feed forward circuit couplings to save and retain data signals during latch mode, static mode, and tristate mode operation while at the same time substantially eliminating static high current I.sub.cct. The clock circuit portions for the latch and flip-flop circuits also are arranged in clock circuit configurations that are free of static current I.sub.cct.

Abstract: An output buffer circuit reduces switching induced noise in integrated circuit devices. A pulldown feed forward circuit is coupled between the input and the output pulldown transistor. The pulldown feed forward circuit bypasses at least some of the intermediate circuit elements of the output buffer circuit. The pulldown feed forward circuit initiates a relatively small sinking current through the output pulldown transistor in response to a first signal at the input before the intermediate circuit elements initiate relatively large sinking current through the output pulldown transistor means. A pullup feed forward circuit is coupled between the input and the output pullup transistor means. The pullup feed forward circuit bypasses at least some of the intermediate circuit elements of the output buffer circuit.

Abstract: To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe.

Abstract: Intermediate path splitting circuit arrangements are coupled between the input node and output stage of an IC defining a plurality of different signal propagation paths. A relatively higher speed output pullup turn on signal progagation path is coupled between the input node and the output pullup transistor element for turning on the output pullup transistor element at relatively higher speed in response to a first input data signal. A relatively slower speed output pulldown turn off signal propagation path turns off the output pulldown transistor element at a relatively slower speed in response to the first data input signal. Similar circuit arrangements are provided for relatively high speed turn on of the pulldown transistor element and relatively low speed turn off of the pullup transistor element. Control of turn on and turn off of the respective output pullup and pulldown transistor elements is from separate output driver nodes for higher speed operation.

Abstract: The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver.

Abstract: Low noise circuits for single stage and multi-stage circuits reduce power rail noise, including both ground noise and supply noise caused by output power rail ground lead and supply lead inductance. Anti-bounce circuits reduce ground bounce by suppressing turn on of the output stage pulldown transistor element during transient occurrence of ground bounce events. Similarly anti-droop circuits reduce output supply V.sub.cc droop by suppressing turn on of the output stage pulldown transistor element during transient occurrence of V.sub.cc droop events. Anti-undershoot circuits dissipate ground undershoot energy by establishing a transient sacrificial current flow through the parasitic output ground tank circuit following transition from high to low potential at the output and by prolonging the sacrificial current flow during transient occurrence of ground undershoot events.

Abstract: A machine provides automated counting of integrated circuit (IC) parts packed in a shipping tube which may be, for example, an opaque shipping rail for translation of the rail along the track. An elongate support or track receives and holds a shipping rail. A first rail sensor positioned adjacent to the track senses the presence of a rail on the support track and generates a start count signal. A second rail sensor positioned along the track generates a stop count signal after the scanning of the rail by the sensors is completed. An IC parts sensor provided by an inductive proximity sensor is positioned adjacent to the track between the first and second rail sensors and senses the presence of IC parts contained in the shipping rail. A roller drive translates the shipping rail and the sensors relative to each other for scanning of the rail by the sensors. The parts sensor generates parts counting signals from the start count signal to the stop count signal.

Abstract: A wind speed and wind direction signal generator includes first and second pulse signal generators each with a respective stator and rotor. The stator for each pulse generator has at least two stator coils mounted at a radial angle relative to each other in the direction of rotation of a rotor so that pulse signals excited on the stationary output lines of the two stator coils are phase shifted relative to each other at a phase detectable angle. The rotor has at least one permanent magnet with two poles spaced from each other for rotation relative to the respective stator coils and for exciting the pulse signals on the stator coil stationary output lines. First and second wind propellers are secured to the respective rotors and are oriented to compass directions at approximately 90.degree. defining a quadrant of a compass coordinate system. The wind propellers cause rotation of the respective rotors at respective frequencies proportional to first and second wind speed components.

Abstract: A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node of an emitter follower transistor element is coupled to a collector node of the input transistor circuit in an inverting coupling. The emitter node is coupled to a base node of the phase splitter transistor element for sourcing base driven current to the phase splitter transistor element in response to data signals at the input. The emitter follower provides transient "overdrive" for fast turn on of the phase splitter. A first clamp circuit between the base node of the emitter follower transistor element and the low potential power rail clamps the base node at a low potential level when the emitter follower transistor element is relatively non-conducting and establishes the input threshold voltage level.

Abstract: An ECL cutoff driver circuit for an ECL gate coupled between ECL high and low potential power rails includes a cutoff clamp circuit. The ECL gate with differential signal inputs and at least one output node is coupled for delivering ECL logic output signals of high and low potential levels during operation of the ECL gate in a switching mode. The cutoff driver circuit includes cutoff transistor elements for shifting down the ECL output at least to a maximum specified cutoff potential level below the ECL logic low potential level in a cutoff state. The cutoff clamp circuit is coupled between the ECL high potential power rail and the output node or output nodes for clamping the ECL output at a minimum or lower bound voltage level substantially at the specified cutoff voltage level V.sub.OLZ. This prevents output buffer transistor elements from being completely turned off for faster return of the ECL gate from the cutoff state to operation in the switching mode.

Abstract: A weather station display system displays weather data on a video monitor, TV receiver or other raster screen display. The weather data is derived from a weather station having multiple weather parameter sensors or transducers for measuring weather parameters and generating electrical signals representative of the measured values of the weather parameters. The electrical signals are conditioned and converted to digitally coded weather data. A microprocessor periodically samples and stores the digitally coded weather data and transfers weather data to a screen memory for raster scanning onto a raster screen display. The microprocessor also loads screen display format data including a main screen display format to the screen memory from program and screen data memory. A light pen coupled to the raster controller permits interrogation of character locations for selectively modifying displayed weather data.