Patents Represented by Attorney Daniel H. Kane
  • Patent number: 5013938
    Abstract: The output enable (OE) cutoff driver gate of a cutoff driver circuit is coupled to receive OE signals of high and low potential and hold an ECL logic gate in the cutoff state in response to one of the high and low OE signals. An OE signal driver circuit provides the OE signals of high and low potential to the OE cutoff driver gate. The OE cutoff driver current sink for sinking current from the OE cutoff driver gate is provided by a current switch circuit for switching sinking current on and off in response to current switch signals of high and low potential in phase with the OE signals. The current switch circuit switches on sinking current when the OE cutoff driver gate is holding the ECL logic gate in the cutoff state. The current switch circuit switches off sinking current for reducing power dissipation when the ECL logic gate is out of the cutoff state. The current switch circuit is provided by a current mirror circuit.
    Type: Grant
    Filed: November 1, 1989
    Date of Patent: May 7, 1991
    Assignee: National Semiconductor Corporation
    Inventor: Julio R. Estrada
  • Patent number: 5012688
    Abstract: A roller conveyor bed is formed by a plurality of driven conveyor spools or rollers rotating in the same direction for conveying and sorting objects. The conveyor rollers define a substantially common conveyor plane along the upper surfaces of the conveyor rollers and are selectively spaced apart for selectively passing objects through the selective spaces between conveyor rollers thereby sorting the objects by a size dimension. An anti-pinch surface is positioned adjacent to each of the conveyor rollers on the downstream side of the conveyor roller with reference to the conveying direction. Each surface is positioned below the conveyor plane and provides an anti-pinch surface which substantially shields the downstream side of the adjacent conveyor roller where the roller surface is turning in a downward direction.
    Type: Grant
    Filed: July 3, 1990
    Date of Patent: May 7, 1991
    Inventor: Malcolm P. Ellis
  • Patent number: 5010701
    Abstract: A corner system for log cabin siding construction over building frame walls and corners gives the appearance of full log construction. Elongate wall siding pieces are applied over the walls with a flat inner side facing the wall and a curved outer side for simulated "log" appearance. Corner siding pieces are applied over the corners with wall covering portions in horizontal alignment with wall siding pieces, and projecting log end portions extend beyond the building corner. Each corner siding piece is cut from a single piece of wood without a joint or seam and with continuous grain between the wall covering portion and the projecting log end portion of a corner siding piece. Wall siding pieces and corner siding pieces are formed with edge configuration of overlapping "ship-lap" siding or interfitting tongue and groove siding.
    Type: Grant
    Filed: December 5, 1989
    Date of Patent: April 30, 1991
    Assignee: Diamond Occidental Forest, Inc.
    Inventors: Brenton S. Halsey, Jr., Arthur C. Larson
  • Patent number: 4988899
    Abstract: An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation threshold operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate for shifting the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate.
    Type: Grant
    Filed: December 11, 1989
    Date of Patent: January 29, 1991
    Assignee: National Semiconductor Corporation
    Inventor: Lars G. Jansson
  • Patent number: 4988898
    Abstract: An ECL/CML to TTL translator circuit couples the output of an ECL/CML gate to the input of a TTL gate. The ECL/CML gate operates with reference to a first power rail higher reference voltage level with transistor elements operating in the non-saturation operating region. The TTL gate operates with reference to a second power rail lower reference voltage level with transistor elements operating in the saturation operating region. The translator circuit includes a reference voltage level shifting constant current non-switching current mirror circuit coupled to the output of the ECL/CML gate. The current mirror circuit shifts the reference voltage level of the ECL/CML gate output from the higher reference voltage level to the lower reference voltage level and delivers a reference voltage level shifted output signal. An operating region translating emitter follower output buffer circuit is coupled to receive the voltage level shifted output signal and drive the input of the TTL gate in the saturation region.
    Type: Grant
    Filed: May 15, 1989
    Date of Patent: January 29, 1991
    Assignee: National Semiconductor Corporation
    Inventor: Lars G. Jansson
  • Patent number: 4979624
    Abstract: A roller conveyor bed is formed by a plurality of driven conveyor spools or rollers rotating in the same direction for conveying and sorting objects. The conveyor rollers define a substantially common conveyor plane along the upper surfaces of the conveyor rollers and are selectively spaced apart for selectively passing objects through the selective spaces between conveyor rollers thereby sorting the objects by a size dimension. An anti-pinch surface is positioned adjacent to each of the conveyor rollers on the downstream side of the conveyor roller with reference to the conveying direction. Each surface is positioned below the conveyor plane and provides an anti-pinch surface which substantially shields the downstream side of the adjacent conveyor roller where the roller surface is turning in a downward direction.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: December 25, 1990
    Inventor: Malcolm P. Ellis
  • Patent number: 4971051
    Abstract: A face mask having a perimeter for sealing against the face of a user is incorporated in a continuous positive airway pressure mask (CPAP) for treatment of central and obstructive sleep disorders. An elongate flexible pneumatic cushion seal is formed around the perimeter of the mask. An air passageway is coupled to the pneumatic air cushion. An inflatable expandable balloon chamber is coupled in open communication through the air passageway to the elongate pneumatic cushion seal. The balloon chamber is inflated to a desired pressure for passage of air between the pneumatic cushion seal and the expandable balloon chamber at said pressure. The pneumatic cushion seal is maintained against the face of a user and follows the changing contours of a user's face by passage of air between the pneumatic cushion seal and the expandable balloon chamber at the desired pressure. This changing volume of air in the pneumatic cushion seal assures that the seal is maintained.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: November 20, 1990
    Inventor: Norman R. Toffolon
  • Patent number: 4972104
    Abstract: An anti-simultaneous conduction transistor is incorporated into the standard TTL circuit totem pole to reduce simultaneous conduction of the pullup and pulldown transistor elements of the totem pole. The collector of the active discharge anti-simultaneous conduction transistor element (Q5) is operatively coupled to a base of the pullup transistor element (Q2,Q3) through a diode (D5), the emitter is coupled to low potential, and the base is coupled to the base of the pulldown transistor element (Q4) through ballast resistance (R6,R7). The anti-simultaneous conduction transistor element (Q5) mirrors the conducting state of the pulldown transistor element (Q4) without current hogging substantially diverting or discharging base current from the base of the pullup transistor element (Q2,Q3) whenever the pulldown transistor element (Q4) is conducting. Undesirable current spikes in the sourcing current are avoided by preventing simultaneous conduction in the totem pole.
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: November 20, 1990
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Julio R. Estrada
  • Patent number: 4962886
    Abstract: Method steps for production of substantially uniform size droplets from a flow of liquid include forming the flow of liquid, periodically modulating the momentum of the flow of liquid in the flow direction at controlled frequency, generating a cross flow direction component of momentum and modulation of the cross flow momentum of liquid at substantially the same frequency and phase as the modulation of flow direction momentum, and spraying the so formed modulated flow through a first nozzle outlet to form a desired spray configuration. A second modulated flow through a second nozzle outlet is formed according to the same steps, and the first and second modulated flows impinge upon each other generating a liquid sheet. Nozzle apparatus for modulating each flow includes rotating valving plates interposed in the annular flow of liquid. The plates are formed with radial slots.
    Type: Grant
    Filed: October 14, 1988
    Date of Patent: October 16, 1990
    Assignee: The Board of Trustees of the University of Maine
    Inventor: Ivar H. Stockel
  • Patent number: 4961010
    Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A separate pulldown delay resistance element of selected value is coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements. The secondary pulldown transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer before the primary pulldown transistor element control terminal lead. A relatively small discharge current is therefore limited from the output before turn on of the relatively large discharge current of the primary pulldown transistor element.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: October 2, 1990
    Assignee: National Semiconductor Corporation
    Inventor: Jeffrey B. Davis
  • Patent number: 4959313
    Abstract: A novel cellular enhancer nucleotide sequence causes expression in undifferentiated stem cells of a flanking exogenous or recombinant gene from a promoter accompanying the gene where the gene and promoter are not normally expressed in the undifferentiated stem cells. In the preferred example the essential or basic core of the cellular enhancer nucleotide sequence is ##STR1## The cellular enhancer may encompass a more general core sequence of approximately, for example, in the range of 300 to 350 bases including the essential or basic core sequence. Recombinant vectors including plasmids and viruses are constructed bearing the novel cellular enhancer flanking a recombinant or exogenous gene and promoter having a specified phenotypic trait to be expressed in undifferentiated stem cells. Propagating cells containing the vector constructs reproduce and propagate the vectors.
    Type: Grant
    Filed: June 22, 1987
    Date of Patent: September 25, 1990
    Assignee: The Jackson Laboratory
    Inventor: Makoto Taketo
  • Patent number: 4958090
    Abstract: Dual phase splitter transistor elements, an output phase splitter transistor element and a secondary phase splitter transistor element, are coupled in current mirror configuration in a TTL output buffer circuit. The output phase splitter transistor element is coupled to the pullup and pulldown transistor elements for controlling the respective conducting states of the pullup and pulldown transistor elements. The collector of the secondary phase splitter transistor element is coupled in a supplemental circuit which can have a variable load without direct connection to the pullup transistor element and output. A low impedance current sourcing active transistor element is coupled in emitter follower configuration at the collector node of the secondary phase splitter transistor element for supplying mirroring current through the emitter of the secondary phase splitter transistor element to reduce current hogging at the dual phase splitter transistor elements.
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: September 18, 1990
    Assignee: National Semiconductor Corporation
    Inventor: Lars G. Jansson
  • Patent number: 4953094
    Abstract: Methods for lofting flat metal starting blanks and for compounding curved metal plates from the flat starting blanks can be used in lofting and fabricating boat hulls, aircraft and automobile bodies, tanks, containment vessels, and other shell structures. The methods relate starting blanks and compounded plates to specified patches of a defined surface having compound curvature, or more precisely, non-zero Gaussian curvature. The surface is a representation of the shell structure to be fabricated by assembling the plates. In each of the methods the in-plane strain is related to instinsic geometry in a strain equation. The strain is explicitly or implicitly considered and solved for accurate and controlled implementation of both the lofting and cutting of the blanks and the compounding of the blank into the desired plate configuration. Solution of the strain equations for boundary nodes in the plane of the blank for cutting the blank minimizes field trim.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: August 28, 1990
    Assignee: Aerohydro, Inc.
    Inventor: John S. Letcher, Jr.
  • Patent number: 4947487
    Abstract: A protective glove is formed of composite material for close fitting over the fingers and the back and palm of the hand. The composite material includes a layer of flexible elastic material for tactile sensitivity through the layer. Optically reflective and dispersive particles are distributed and embedded within the layer for dispersing incident laser light thereby preventing laser burn injuries to the hand of a wearer.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: August 14, 1990
    Assignee: The Jackson Laboratory
    Inventors: Jeffrey D. Saffer, Louis A. Profenno
  • Patent number: 4947058
    Abstract: A transient voltage difference circuit is coupled into a TTL current sinking output circuit for transient performance enhancement during transition from high to low level potential at the output. The TTL output circuit includes a pulldown transistor element for sinking current from an output node to low potential, a base drive transistor for driving the base of a current sinking pulldown transistor element, an input base node of the base drive transistor coupled to receive input signals of high and low level potential, and a voltage clamp network coupled between the input base node and low potential for maintaining a potential level at the input base node sufficient to turn on the base drive transistor. An RC network is coupled between the input base node and low potential.
    Type: Grant
    Filed: June 3, 1988
    Date of Patent: August 7, 1990
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Roy L. Yarbrough, Julio R. Estrada
  • Patent number: 4945265
    Abstract: A pseudo-rail circuit is coupled between the differential output gate or buffer of an emitter coupled logic or current mode logic (ECL/CML) circuit and the high potential level power rail. The pseudo-rail circuit provides a pseudo-rail node. A first clamp circuit is coupled to the pseudo-rail node for clamping the pseudo-rail node at a first potential level in response to a first control signal. A second clamp circuit is coupled to the pseudo-rail node for clamping at a second potential level in response to a second control signal. A clamp switching circuit alternately applies the first and second clamp circuits to the pseudo-rail node in response to the control signals. As a cutoff driver circuit, the first clamp circuit of the pseudo-rail circuit applies the high potential level of the power rail to the pseudo-rail node. The second claim circuit pulls down the pseudo-rail node to hold the output of the differential output gate in the cutoff state.
    Type: Grant
    Filed: July 13, 1989
    Date of Patent: July 31, 1990
    Assignee: National Semiconductor Corporation
    Inventor: Julio R. Estrada
  • Patent number: 4945263
    Abstract: A TTL to ECL/CML translator circuit delivers differential or complementary ECL logic output signals in response to TTL input signals with voltage gain, small output voltage swing and with a narrow transition region. The TTL input circuit is coupled to a current mirror circuit with first and second current mirror branch circuits. A differential amplifier gate circuit with differential amplifier first and second gate transistor elements co-acts with the current mirror circuit. The second current mirror branch circuit also constitutes the differential amplifier first gate transistor element. A threshold clamp circuit applies a threshold voltage level at the base node of the differential amplifier second gate transistor element thereby establishing a TTL input threshold at the threshold voltage level. First and second ECL output circuits are coupled to the collector nodes of the differential amplifier first and second gate transistor elements for delivering complementary ECL output signals.
    Type: Grant
    Filed: August 23, 1989
    Date of Patent: July 31, 1990
    Assignee: National Semiconductor Corporation
    Inventor: Julio R. Estrada
  • Patent number: 4943741
    Abstract: An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potential to respective true and complementary outputs of the ECL/CML gate. The emitter follower current switch circuit effectively disconnects the output current sink from and ECL/CML gate output and corresponding output buffer emitter follower transistor element when the corresponding output is at high potential. At each output a current switch transistor element is coupled between the respective output buffer emitter follower transistor element and the output current sink. A control circuit controls the conducting state of the current switch transistor element so that it is on (conducting) or off (non-conducting) for corresponding output signals of low and high potential respectively.
    Type: Grant
    Filed: May 24, 1989
    Date of Patent: July 24, 1990
    Assignee: National Semiconductor Corporation
    Inventors: Julio R. Estrada, Roy L. Yarbrough
  • Patent number: 4921301
    Abstract: A portable and foldable maternity lounger is constructed with a three section folding frame and a frame cover of three portions. A head end portion and a foot end portion are formed in the configuration of pockets or envelopes of firm non-stretching material open on sides facing each other for sliding respectively over the ends of the frame. A mid portion substantially covers the mid section of the frame. The mid portion of the frame cover is formed by a lower panel of firm non-stretching material for supporting hips and an upper panel of elastic stretching material for expandable support of the abdomen. The upper and lower panels are joined by a continuous seam in the middle to form a continuous mid portion without uncomfortable exposure of the abdomen. The upper panel is formed with a border of firm substantially non-stretching material to distribute weight to the elastic stretching material.
    Type: Grant
    Filed: January 25, 1988
    Date of Patent: May 1, 1990
    Inventor: R. Jalaine Haynes
  • Patent number: RE33345
    Abstract: Secondary winding configurations and methods particularly applicable for toroid transformers are described for winding secondary windings over the indexed primary winding and toroidal core. The secondary winding is formed in the configuration of a multifilar winding of a plurality of coplanar parallel filaments with a first elongate strip of electrically insulating material bonded to the filaments on one side and a second elongate strip of electrically insulating material bonded to the filaments on the other side and to the first elongate strip. The resulting electrically insulated multifilar strap winding contains the filaments in substantially parallel coplanar relationship. The mulfifilar strap winding is wound around the toroidal core in substantially equally spaced turns. The strap winding maintains the filaments substantially in equally spaced relationship relative to each other over irregular surfaces and compound curvature of the toroidal core without crossover.
    Type: Grant
    Filed: June 30, 1987
    Date of Patent: September 18, 1990
    Assignee: GFS Manufacturing Company, Inc.
    Inventors: Robert D. Sylvester, Jr., Paul C. Horn, Vincent J. Bober