Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit using a filtering time delay in generating a detection signal with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time delay is controlled with the power transistor switching time.

Abstract: A telephone receiving section having a final stage, an electroacoustic transducer having a first terminal connected to the ground of the circuit, a unit for controlling switching on/off, a source of a reference voltage, a switch that can adopt a first position or a second position in order to connect the second terminal of the transducer selectively, via a capacitor, to a reference-voltage terminal of the reference voltage source or to an output terminal of the final stage, respectively, and control means that respond to signals of the unit for controlling switching on/off in order to activate or to deactivate the final stage and the reference-voltage source and to operate the switch in accordance with a predetermined time program. The receiving section operates with the same immunity to disturbances as a fully balanced structure, even though the transducer is not connected between two balanced outputs.

Abstract: A circuit for detecting signals present on a bifilar voltage-supply and signal-transmission line, in which the signals are constituted by positive and negative variations of the supply potential of at least one of the wires of the line, the circuit including a low-pass filter connected to the two wires of the line in order to supply, at an output terminal of the filter, a constant reference potential substantially equal to the supply potential of a preselected one of the two wires, a first threshold comparator having a reference input terminal and a threshold input terminal connected, respectively, to the output terminal of the filter and to the preselected wire of the two wires, and a second threshold comparator having a reference input terminal and a threshold input terminal connected, respectively, to the preselected wire of the two wires and to the output terminal of the filter.

Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.

Abstract: The integrated device for microfluid thermoregulation comprises a semiconductor material body having a surface; a plurality of buried channels extending in the semiconductor material body at a distance from the surface of the semiconductor material body; inlet and outlet ports extending from the surface of the semiconductor material body as far as the ends of the buried channels and being in fluid connection with the buried channels; and heating elements on the semiconductor material body. Temperature sensors are arranged between the heating elements above the surface of the semiconductor material body.

Abstract: An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received.

Abstract: A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.

Abstract: A method of fabricating or designing a control unit for electronic microcontrollers or microprocessors that includes fabricating a finite state machine having at least one combinatorial network, the finite state machine having a plurality of control sub-units, each structured to correspond to one combinatorial logic network. Each unit in the plurality of control sub-units is independently connected to an arbitration block to provide information about a possible future state and receive a present state command.

Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

Abstract: Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

Abstract: The method for authentication and electronic signature is of the private-key, challenge and response type between a user requesting an authorization, via, for example, a smart card and a controller—check terminal—supplying the authorization. To increase security of the authorization or authentication operations, the smart card comprises a chaotic generator generating user's acknowledgement code, which is compared with a comparison code generated by the check terminal using a chaotic generator which is the same.

Abstract: An SMPS converter with an inductor connected in series to the standard inductor present in the output filter to form an inductive divider supplying an intermediate voltage having an amplitude greater than the output voltage. The intermediate voltage is supplied to a capacitor that stores the voltage during the conduction phase of the integrated circuit that forms the switch of the converter and transfers the voltage during opening of the integrated circuit to a capacitor connected between the output and the supply input of the integrated circuit.

Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (VC) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (VC) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (IDAC) of the digital-analog converter such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter keeps the filter voltage (Vf) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.

Abstract: A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a layer of silicide on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining stack gate regions and HV gate regions of high-voltage transistors; and forming HV source and drain regions and cell regions.

Abstract: A switched capacitor digital-to-analog converter includes a first voltage generator for providing first and second reference voltages, a second voltage generator for providing third and fourth reference voltages selected to match predetermined design values of the first and second reference voltages, and an array of binary weighted capacitors. Each capacitor has a first electrode connected to a common circuit node, which is connected to a converter output terminal and a second electrode selectively connected, through an associated first switching circuit, to either one of the first and second reference voltages or, through an associated second switching circuit, to either one of the third and fourth reference voltages.

Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

Abstract: A method of improving the signal/noise ratio of a sigma-delta modulator during the re-establishment of its stability that includes: defining a bit sequence corresponding to a state of instability of the modulator, monitoring the flow of bits output by the modulator to check whether it contains the instability bit sequence, and resetting the modulator to zero if the instability bit sequence is detected at the output. To ensure a high signal/noise ratio of the modulator even during the detection and re-establishment of stability, the method also includes: delaying the flow of bits output by the modulator at least for the time required to detect the instability bit sequence and modifying the output bit sequence during the delay period by replacing it with a predetermined bit sequence.

Abstract: A circuit for providing a minimum wake-up time, in which a monostable circuit generates the WAKE-UP signal for a time at least as long as a minimum time established by the monostable circuit. The circuit is structured to extend the WAKE-UP signal for a time necessary to equal the minimum time that is established by the monostable circuit and to disable the WAKE-UP signal at the end of the variation of the input signal of the device being controlled.

Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.