Abstract: A vertical capacitor structure fabricated in a semiconductor substrate region overlaid by a buried oxide layer and a buried doped layer, as well as by a semiconductor layer that includes a sinker doped region in contact with the buried doped layer, wherein an oxide trench structure is formed, this oxide trench structure being filled with suitably doped polysilicon to produce, in combination with the sinker region, the plates of the vertical capacitor structure, with the oxide trench structure forming the dielectric therebetween. A process for integrating a vertical capacitor structure starting from a structure blank that includes a semiconductor substrate, a buried oxide layer and a buried doped layer is also provided.

Abstract: A switched mode power supply having a first circuit provided with a primary winding of a transformer to which a pulse voltage is applied, a second circuit having a secondary winding of the transformer, a reactor provided with a magnetic core and which has a terminal connected to a terminal of the secondary winding, at least one filter provided with input and output terminals and a first diode connected in parallel to the input terminals of the filter is shown. The other terminal of the reactor is connected to a terminal of the first diode. The power supply includes a second diode that has a first terminal connected to the other terminal of the first diode and a second terminal connected to the other terminal of the secondary winding and a control circuit coupled to an output terminal of the filter and to the other terminal of the secondary winding. The control circuit generates a current able to reset the magnetic core of the reactor.

Abstract: A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Abstract: A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity.

Abstract: A method and apparatus for determining parameters for coupling of channels in a digital audio encoder. A frequency range of two audio channels is coupled together in a coupling channel, and a systematic method of determining optimum coupling parameters is employed. Sub-bands of the channels are processed individually, and a measure of the power of each sub-band is used to determine a coupling coefficient generation scheme for each individual sub-band. Adjacent ones of the sub-bands using the same coupling scheme are combined to form bands in the coupling channel, which dictate the generation of the coupling coordinates for the audio channels. The arrangement of the sub-bands in bands also facilitates the generation of phase flags for each band, on the basis of the coupling scheme used in the band.

Abstract: A non-volatile semiconductor memory device that includes an address buffer block, a matrix of memory cells, and an output buffer block. The address buffer block receives input signals external to the memory device, that in a first operating mode are controlled by devices outside to the memory device, and transmit signals to the matrix of memory cells, which are adapted to decode the received signals and to transmit in turn output decoded signals through the output buffer block. A command block is provided that is activatable through an external control signal and once activated, it puts the memory device in a second operating mode in which the command block receives at least a part of the signals in output of said matrix of memory cells and, after having processed them, transmits internal address signals to the address buffer block. This provides a feedback inside the memory device capable of making the same able to autonomously execute a succession of instructions stored in the matrix of memory cells.

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

Abstract: A sensing device having a microelectromechanical structure made of semiconductor material, and a control loop for controlling the microelectromechanical structure, the microelectromechanical structure including a stator element and a rotor element electrostatically coupled together, and the control loop including a position interface supplying a position signal indicative of the position of the rotor element, and a one-bit quantizer receiving the position signal and supplying a corresponding bit sequence. The sensing device further includes a calibration device for calibrating the microelectromechanical structure, including a microactuator made of semiconductor material and coupled to the rotor element, and a driving circuit for driving the microactuator, and receiving the bit sequence and supplying to the microactuator a driving signal correlated to a mean value of the bit sequence in a given time window.

Abstract: A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on the first areas, HV oxide regions on the second areas, selection oxide regions, tunnel oxide regions, and matrix oxide regions on the third areas; forming floating gate regions and insulating regions on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions laterally to the LV gate regions; forming silicide regions on the first source and drain regions and on the LV gate regions; forming semiconductor material regions completely covering the second and third areas; and at the same time forming HV gate regions on the HV oxide regions, forming selection gate regions on the selection oxide regions, and forming control gate regions on the insulating regions through shaping of the semiconductor material regions.

Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Abstract: A charge pump having a phase-generator circuit generating phase signals and an oscillator circuit supplying a clock signal, a current-limitation circuit to limit the current flowing in the oscillator circuit, and a control circuit supplying on an output a control signal supplied to the current-limitation circuit. The control circuit has a first current mirror connected to a ground line, a second current mirror connected to a supply line, a cascode structure arranged between the first and the second current mirrors and connected to the output of the control circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line, and a compensation circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line and by slow variations in temperature.

Abstract: A low consumption oscillator having an inverter connected to a high supply potential and to a low supply potential via two respective resistors, with the resistors formed of capacitors having strong leakages.

Abstract: A manufacturing process providing a zener diode formed in an N-type well housing a first N-type conductive region and having a doping level higher than the well, and a second P-type conductive region arranged contiguous to the first conductive region. The first conductive region is connected, through a third N-type conductive region having the same doping level as the first conductive region, to a conductive material layer overlying the gate oxide layer to be protected. The third conductive region, the well, and the substrate form an N+/N/P diode that protects the gate oxide layer during manufacture of the integrated device from the deposition of the polycrystalline silicon layer that forms the gate regions of the MOS elements.

Abstract: A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Abstract: A switch-type regulator with a soft-start function having an output terminal supplying an output voltage, and including an error amplifier, having a first input receiving a constant reference voltage, a second input receiving a feedback voltage dependent on the output voltage, and supplying a compensation terminal with an error voltage correlated to the difference between the reference voltage and the feedback voltage. The error amplifier includes a differential amplifier. The regulator also includes a compensation network connected to the compensation terminal. A soft-start function is obtained exploiting the compensation network.

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon t

Abstract: An inertial sensor having a stator and a rotor made of semiconductor material and electrostatically coupled together, and a microactuator also made of semiconductor material, coupled to the rotor and controlled so as to move the rotor itself and thus compensate for the position offset thereof.

Abstract: The present invention relates to an amplifier having a fan-out which varies according to the time spent between an edge of a propagation signal and an edge of a logic input signal, the amplifier including several identical blocks, each block having an output stage connected between a data input and a data output, the data input and output being respectively connected to the data inputs and outputs of the other blocks; a delay element, the delay elements of all blocks being connected in series, the delay element of the first block receiving the synchronization signal; an edge detector, the input of which is connected to the input of the output stage; and means for inhibiting the propagation of the synchronization signal through the delay element when the signal generated by the edge detector of the preceding block is active and for activating the output stage and the edge detector when the signal generated by the delay element of the preceding block is active.

Abstract: A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.