Abstract: A sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22). A sensing element (14) is located inside the cavity (31) while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity (31). The filter (22) protects the sensing element (14) from physical damage and contamination during die singulation and other assembly processes. The filter (22) also improves the chemical sensitivity, selectivity, response times, and refresh times of the sensing element (14).

Abstract: A non-zero temperature coefficient of offset (Tco) in a semiconductor device (5) is adjusted by reducing the amount of adhesive material used to secure a first structure to a second structure. An adhesive layer (14) used to secure a sensor die (11) to a constraint die (12) in a pressure sensor application is reduced in thickness and/or formed so that adhesive material does not completely cover the constraint die (12). The Tco is further adjusted by reducing the amount and/or patterning the adhesive layer (18) used to secure the sensor (10) to its package (16).

Abstract: A semiconductor component can be manufactured by providing a leadframe (12) with leads (13) and a flag (14) substantially coplanar with at least one of the leads (13) wherein the flag (14) has a hole (15). An electronic substrate (11) is adhered to the flag (14) wherein a perimeter of the electronic substrate (11) has bonding pads (21), wherein the bonding pads (21) face toward the flag (14), wherein the electronic substrate (11) covers the hole (15), and wherein the flag (14) is absent over the bonding pads (21). Next, the pads (21) are wire bonded to the leads (13), and then the electronic substrate (11) and the leadframe (12) are encapsulated with a packaging material (17) wherein the packaging material (17) has an opening (23) and is devoid of covering the hole (15) in the flag (14).

Abstract: A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.

Abstract: An optical semiconductor component (10) includes a substrate (11) having a surface (12), a photodetector (13) supported by the substrate (11), and a seismic mass (21) overlying the surface (12) of the substrate (11) and overlying a portion of the photodetector (13). The seismic mass (21) has a hole (22) overlying a base region (32) of the photodetector (13) wherein the seismic mass (21) is movable relative to the substrate (11) and the photodetector (13).

Abstract: A semiconductor component includes a leadframe (11, 40) having leads (12, 41) and a ground plane (13, 42) wherein the ground plane (13, 42) has an opening (15, 45). A semiconductor substrate (21) is located in the opening (15, 45) and is approximately coplanar with the ground plane (13, 42). The coplanarity shortens the ground plane wire bonds (23) and improves the electrical performance of the semiconductor component.

Abstract: A method of manufacturing a semiconductor component includes forming a vertical side seal for a runner in a first mold plate by mating a protrusion of the first mold plate with a protrusion of a second mold plate. As an encapsulating material is forced through the runner, the vertical side seal prevents an encapsulating material from leaking out of the edge of the runner.

Abstract: A heat dissipation apparatus (51) has a lid (12) and an optimized fin arrangement (16) located in a cavity (57) of a base (11). Semiconductor chips (41, 42, 43, 44, 45, and 46) are coupled to the lid (12), and a heat conducting medium (47) is forced into the cavity (57) through a port (13) and out of the cavity (57) through a different port (14). Heat generated by the semiconductor chips (41, 42, 43, 44, 45, and 46) is thermally conducted into the fin arrangement (16) and then transferred into the heat conducting medium (47).

Abstract: A semiconductor component includes a leadframe (10), an electronic component (21) mounted over the leadframe (10), a packaging material (23) around the electronic component (21) and the leadframe (10) wherein the packaging material has a recess (24), another electronic component (30) in the recess (24), and a cap (32) over the recess (24) and the other electronic component (30). The other electronic component (30) is electrically coupled to the electronic component (21) through internal leads (13) and (14) of the leadframe (10). After a dam bar (15) is removed from the leadframe (10), the internal leads (13) are physically and electrically isolated from other portions of the leadframe (10) including the external leads (12) and the flag (11).

Abstract: A method of passivating a semiconductor substrate includes singulating (13) a semiconductor substrate (23) from a semiconductor wafer, coupling (14) a heatsink (21) to the semiconductor substrate (23), etching (15) the semiconductor substrate (23) in a chamber of an etch tool, and passivating (17) the semiconductor substrate (23) with an oxide layer (31). The semiconductor substrate (23) is kept in the chamber of the etch tool from the etching (15) step through the passivating (17) step. The etching (15) of the semiconductor substrate (23) does not substantially etch the heatsink (21), and the passivating (17) of the semiconductor substrate (23) does not substantially passivate the heatsink (21).

Abstract: A method for making a semiconductor structure which may be subject to small particle contaminants (12) includes pre-reacting the small particle (12) with a substrate (10) at a reaction temperature (27, 28). Pre-reacting the particle's (12) greatly reduces the particles' susceptibility to further reaction during subsequent processing, particularly gate dielectric formation. Consequently, the pre-reacted particle (13) as well as the remainder of the structure surface (11) can be covered with a high quality conformal deposited dielectric (14) which maintains a uniform thickness. Potential localized high leakage current density regions are thereby reduced. Additionally, an undesirably thin gate oxide region (70) adjacent a thick field oxide region (66) of a typical MOS structure is eliminated. Yield and reliability are thereby enhanced.

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Abstract: An electronic component can be more easily tested after being mounted onto a circuit board (660). The component also stops cracks from propagating over vital areas of a substrate (110). The component includes an electrically insulative substrate (100), electrically conductive traces (120) supported by the electrically insulative substrate (100), and an electrically insulative layer (310) covering inner and outer portions of the electrically conductive traces (120) while middle portions of the electrically conductive traces (120) remain exposed.

Abstract: A semiconductor sensing device (10) for sensing a lateral acceleration includes a field effect transistor (132) fabricated along a sidewall (114) of a trench (112) formed in a substrate (11). A movable gate (12) overlies a channel region (138) of the field effect transistor (132). In response to a lateral acceleration perpendicular to the sidewall (114) of the trench (112), the movable gate (12) moves relative to the substrate (11) in a direction substantially perpendicular to the sidewall (114). The conductive state of the channel region (138) depends on the distance between the movable gate (12) and the channel region (138) and changes in response to the lateral acceleration Thus, the motion of the movable gate (12) modulates a current flowing in the field effect transistor (132). The lateral acceleration is sensed by sensing the current flowing in the field effect transistor (132).

Abstract: An electronic component (10) has an electrically insulating substrate (20) that is encapsulated with an electrically conductive material (15) to provide thermal dissipation for the electronic component (10). The electrically insulating substrate (20) has cavities (21-24) that are either completely filled with an electrically conductive material (15) or are partially filled to provide recesses (26-27) for electronic devices (30,31). The electronic devices (30,31) are electrically coupled to the leads (60-63) of the electronic component (10) using either wire bonds (70) or metallic depositions (55-57).

Abstract: A method of operating chemical sensors (21) uses synchronously pulsed signals to reduce the power consumption of the chemical sensors (21). A first voltage source can be used to control and to heat multiple heating elements of the chemical sensors (21). The first voltage source can also be used to control other sensors which do not require elevated temperature operation. A second voltage source can be used to operate and bias the chemical sensors (21) heated by the multiple heating elements. Power consumption is reduced by turning or pulsing off the heating element (16) when it is not used.

Abstract: In a tape lead bonding system, lead frames (3) are moved on a tape substrate (2) from a first station, where a first camera (12) takes an image of one half of one lead frame, to the next station, where a second camera (16) takes an image of the second half of the lead frame, while, at the same time, the first half of the next lead frame is being imaged by the first cameras(12). Both images of the particular lead frame (3) are then inspected by an inspection computer (15) before that lead frame reaches a bonding station so that bonding of a semiconductor die (21) to the lead frame (3) can be halted if a defect in the lead frame (3) is found. The system operates at the speed of the bonding unit (22), with out requiring the system to be slowed down to allow a full inspection of each lead frame (3) before the bonding step.

Abstract: A high performance, high voltage non-epi bipolar transistor including a substrate (12) with an n-type conductivity well (13) and an insulative layer (14) with first (15), second (17) and third (18) openings exposing the substrate in the well. A first p-type volume (19) surrounding the first and second openings (15, 17) beneath the insulative layer (14), and a second n-type volume (22) surrounding the third opening (18) beneath the insulative layer (14). A p-type intrinsic base (25) in the first opening (15) and in contact with the first volume (19). A p-type extrinsic base (30) in the second opening (17) and in contact with the first volume (19). An n-type collector (32) in the third opening (18) and in contact with the second volume (22), and an n-type emitter layer (27) in the first opening in overlying contact with the intrinsic base (25).

Abstract: A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation.

Abstract: An electronic component (10) for aligning a light transmitting structure (19) such as an optical fiber or a waveguide, includes a semiconductor substrate (11) which contains or supports at least one semiconductor device (12). To provide electrical isolation and mechanical protection for the semiconductor device (12), a passivation layer (25) is disposed over the semiconductor substrate (11). At least one alignment feature (14) for the light transmitting structure (19) is provided over the passivation layer (25) and over the semiconductor device (12). The alignment feature (14) is manufactured simultaneously during a flip chip bump process which eliminates the necessity for extra processing steps while providing additional alignment functionality.