Abstract: An electronic component includes a substrate (11) having a device surface (13) and opposite ends (14, 15) adjacent to the device surface (13), an electronic device (16) supported by the device surface (13), and an interconnect substrate (30) overlying a first end (14) of the substrate (11) and electrically coupled to the electronic device (16). The electronic component can be manufactured by inserting the second end (15) of the substrate (11) into one of a plurality of holes (23) in a carrier (20) wherein the device surface (13) and the carrier (20) form an angle greater than approximately five degrees.

Abstract: A method of etching a semiconductor substrate (11) includes thinning (102) the semiconductor substrate (11), providing (103) a support layer (30) for the semiconductor substrate (11), providing (104) an etch mask (28) over the semiconductor substrate (11), and etching (105) the semiconductor substrate (11) using an etchant mixture of hydrofluoric acid, nitric acid, phosphoric acid, sulfuric acid, and a wetting agent at a temperature below ambient. The method is capable of using one etch step (105) and one etch mask (28) to form a plurality of trenches (12, 13) having the same width (15, 17) but different depths (16, 18) and different orientations. The method can be used to singulate different sizes and configurations of semiconductor dice from the semiconductor substrate (11).

Abstract: A metallization system (19) for a semiconductor component (20) includes depositing a dielectric layer (12) over a substrate (10), etching a via (14) in the dielectric layer (12), sputtering a metal layer (17) of aluminum, copper, and tungsten over the dielectric layer (12) and in the via (14), and sputtering a different metal layer (18) of aluminum and copper over the first metal layer (17) and in the via (14). The metallization system (19) reduces the reliability issues associated with electromigration and stress migration while enhancing the ability to fill vias with large aspect ratios.

Abstract: A method of fabricating a sensor (100) includes providing a substrate (200), providing a stationary comb structure (117, 118) overlying the substrate (200), providing a movable seismic mass (101) overlying the substrate (200) and movable relative to the substrate (200) and the stationary comb structure (117, 118), and providing a dielectric layer (500, 800) between the stationary comb structure (117, 118) and the movable seismic mass (101). The dielectric layer (500) increases the sensitivity of the sensor (100) and also prevents the movable seismic mass (101) from shorting together with the stationary comb structure (117, 118).

Abstract: A sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22). A sensing element (14) is located inside the cavity (31) while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity (31). The filter (22) protects the sensing element (14) from physical damage and contamination during die singulation and other assembly processes. The filter (22) also improves the chemical sensitivity, selectivity, response times, and refresh times of the sensing element (14).

Abstract: An assembly substrate includes a substrate (11, 31, 41), a composite layer (12, 32, 42) overlying the substrate (11, 31, 41), and an electrically conductive layer (13, 33, 43) overlying the composite layer (12, 32, 42). The composite layer (12, 32, 42) includes a first material having an as-deposited tetragonal crystal structure and a second material. The second material in the composite layer (12, 32, 42) reduces the susceptibility of the composite layer (12, 32, 42) to fracture under stress.

Abstract: A polymeric organic coating (24) used to package a semiconductor component (10) increases voltage isolation, decreases thermal resistance, and increases scratch and abrasion resistance for the semiconductor component (10). The coating (24) is applied to a leadframe (14) of the semiconductor component (10) using a chemical grafting process that involves the use of monomers, prepolymers, a catalyst, a graft initiator, and other ingredients. The coating (24) forms a polymeric organic film that is chemically bonded to the surfaces of the leadframe (14). The chemical grafting process produces a chemical bond, which improves adhesion between the coating (24) and the leadframe (14).

Abstract: A semiconductor device (10) includes a semiconductor substrate (11) underlying an oxide layer (12). A layer (13) comprised of titanium overlies the oxide layer (12). The oxide layer (12) improves the adhesion of the layer (13) comprised of titanium to the semiconductor substrate (11).

Abstract: A method of forming a spacer (41) around a gate electrode (32) includes sequentially disposing a first layer (48), a second layer (36), and a third layer (37) of dielectric over a semiconductor substrate (31) and over the gate electrode (32) and, thereafter, sequentially etching the third (37), second (36), and first (48) layers. The third layer (37) is etched with a first etchant to define a width (51) for the spacer (41). The first etchant selectively etches the third layer (37) versus the second layer (36). Etching the third layer (37) does not expose the first layer (48) located beneath the second layer (36). A second etchant, which is different from the first etchant, is used to selectively etch the second layer (36) versus the first layer (48). Etching the second layer (36) does not expose the semiconductor substrate (31) located beneath the first layer (48).

Abstract: A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

Abstract: An improved edge termination scheme for semiconductor structures includes field-limiting rings (13, 14 and 15) having a fine-to-coarse incrementing scheme (18, 19 and 20) which is spatially additive assuring constancy against lateral junction variation. This spatially increasing scheme greatly enhances breakdown voltage characteristics. Additionally, redundant rings (14) are used to further guarantee insensitivity of the device to manufacturing variations. Reverse floating polysilicon flaps (28, 29 and 30) may be included to aid surface stability, when exposure to stray surface charges is anticipated. Additionally, this scheme provides for easy voltage scalability.

Abstract: A semiconductor wafer contact system includes a sealed bladder (32) containing incompressible material. The sealed bladder (32) presses against a flexible circuit layer (28) including an array of electrical contacts (30). The bladder (32) forces the array of electrical contacts (30) against a corresponding array of device electrical contacts (12) on die (11) of a semiconductor wafer (10). The bladder (32) adapts in shape to compensate for die level and wafer level irregularities in contact height and non-parallelism. Additionally, bladder (32) ensures a constant force between membrane contacts (30) and die contacts (12), across the entire wafer (10).

Abstract: A method of manufacturing a semiconductor component includes sputtering a first metal layer (16) over a substrate (11), sputtering a second metal layer (17) over the first metal layer (16), selectively etching the second metal layer (17) versus the first metal layer (16), selectively etching the first metal layer (16) versus the second metal layer (17), and thereafter, selectively re-etching the second metal layer (17) versus the first metal layer (16).

Abstract: An interconnect system (31) includes an interconnect bump (29) over an under bump metallurgy (25). The under bump metallurgy (25) includes a barrier layer (26) having a barrier material such as titanium, an adhesion layer (28) having an adhesion material such as copper, and a mixture layer (27) having both the barrier material and the adhesion material. The mixture layer (27) is located between the barrier layer (26) and the adhesion layer (28), and the adhesion layer (28) is located between the mixture layer (27) and the interconnect bump (29). The interconnect bump (29) contains solder and is used as an etch mask when patterning the under bump metallurgy (25).

Abstract: A high frequency semiconductor component (10) includes a first substrate (12) having a first surface (13) opposite a second surface (14), a first electrically conductive layer (16) supported by the first surface (13) of the first substrate (12), a second electrically conductive layer (17) supported by the second surface (14) of the first substrate (12) wherein the second electrically conductive layer (17) is electrically coupled to the first electrically conductive layer (16), a second substrate (19) having a first surface (20) and a second surface (21), a third electrically conductive layer (22) supported by the first surface (20) of the second substrate (19), and an electrically insulating layer (23) between the second and third electrically conductive layers (17, 22) wherein the second and third electrically conductive layers (17, 22) are electrically coupled together through the electrically insulating layer (23).

Abstract: A high performance, high voltage non-epi bipolar transistor including a substrate (12) with an n-type conductivity well (13) and an insulative layer (14) with first (15), second (17) and third (18) openings exposing the substrate in the well. A first p-type volume (19) surrounding the first and second openings (15, 17) beneath the insulative layer (14), and a second n-type volume (22) surrounding the third opening (18) beneath the insulative layer (14). A p-type intrinsic base (25) in the first opening (15) and in contact with the first volume (19). A p-type extrinsic base (30) in the second opening (17) and in contact with the first volume (19). An n-type collector (32) in the third opening (18) and in contact with the second volume (22), and an n-type emitter layer (27) in the first opening in overlying contact with the intrinsic base (25).

Abstract: An optical system (22) contains an optical waveguide (10) having cladding layers (11, 12) defining a channel (19) that is filled with an optically conductive core material (20). The index of refraction of the optically conductive core material (20) is greater than the index of refraction of the cladding layers (11, 12) to maintain total internal reflection of an input light beam (39). The channel (19) is tapered at an angle (32) to increase beam divergence of the input light beam (39). The beam divergence is increased while the input light beam (39) is reflected through the optically conductive core material (20) from an opening (26) to an exit (27) of the channel (19). The taper of the channel (19) maintains an adiabatic characteristic for the waveguide (10).

Abstract: A multi-directional optocoupler includes an assembly substrate (11), an emitter (20) coupled to a first region of the assembly substrate (11), a different emitter (21) coupled to a second region of the assembly substrate (11), a detector (23) coupled to a third region of the assembly substrate (11), a different detector (22) coupled to a fourth region of the assembly substrate (11), a light transmissive region (24) coupling the emitter (20) and the detector (23) wherein the emitter (20) and the detector (23) are configured to transmit and receive a first signal in a direction (26), and a different light transmissive region (25) coupling the different emitter (21) and the different detector (22) wherein the different emitter (21) and the different detector (22) are configured to transmit and receive a second signal in a different direction (27).

Abstract: An optical isolator (10) includes an opto-electronic emitter (16) and an opto-electronic detector (17) mounted over offset portions (12, 13) of a leadframe (11). The offset portions (12, 13) form angles (14, 15) with other portions (24, 25) of the leadframe (11). An optically transmissive material (22) encapsulates the opto-electronic emitter (16) and the opto-electronic detector (17), and a reflective material (20) is located above the opto-electronic emitter (16) and the opto-electronic detector (17). An optically insulative packaging material (26) encapsulates the optically transmissive material (22).

Abstract: A resonator includes a substrate (15) having a first dielectric constant, an insulative layer (16, 31) overlying the substrate (15) and having a second dielectric constant wherein the second dielectric constant is lower than the first dielectric constant, and a electrically conductive layer (11) overlying the insulative layer (16, 31). The resonator has a higher "Q" factor than the prior art.