Abstract: An electronic component with reduced capacitance includes a substrate (12) with an interconnect line (14), an additional substrate (11) with an interconnect line (13) wherein the substrate (12) overlies the additional substrate (11), an electronic device (15) overlying the substrate (12) and electrically coupled to the interconnect line (14) of the substrate (12), and an additional electronic device (17) having a lead (23) and an additional lead (26) wherein the lead (23) overlies the substrate (12) and is electrically coupled to the interconnect line (14) of the substrate (12) and wherein the additional lead (26) overlies the additional substrate (11) and is electrically coupled to the interconnect line (13) of the additional substrate (11).

Abstract: An apparatus and a method of dynamically mixing a slurry for a chemical mechanical polish includes pumping an abrasive (33) and an oxidizer (37) into a first portion (19) of a slurry mixer (11), using a magnetically coupled stirrer (17) to blend the abrasive (33) and the oxidizer (37) into a slurry (41) in the first portion (19) of the slurry mixer (11), transporting the slurry (41) through a diffuser (21) and into a second portion (22) of the slurry mixer (11), keeping the slurry (41) in the second portion (22) of the slurry mixer (11) for a residence time, and, subsequently, using the slurry (41) to chemical mechanical polish a semiconductor substrate (43). The diffuser (21) reduces air entrainment of the slurry (41), and the residence time enables the slurry (41) to be used when it has a maximum polishing rate.

Abstract: A hybrid multi-chip module includes semiconductor chips (27, 31) bonded to a base plate (24). The base plate includes a substrate (11) having two surfaces (12, 13) and a conductive material (16) molded on the two surfaces (12, 13). A coefficient of thermal expansion (CTE) mismatch between the substrate (11) and the conductive material (16) at the first surface (12) is balanced by a similar, but opposite, CTE mismatch between the substrate (11) and the conductive material (16) at the second surface (13). The CTE mismatch balance across the base plate (24) produces a base plate (24) having a substantially planar form at high temperatures.

Abstract: A semiconductor diode device (10) includes two heatsinks (11, 12), a semiconductor substrate (15) having a p-n junction (35) and located between the two heatsinks (11, 12), solder (13, 14) between the heatsinks (11, 12) and the semiconductor substrate (15), and a packaging material (16) covering the semiconductor substrate (15), the solder (13, 14), and a portion of the two heatsinks (11, 12). The two heatsinks (11, 12) each have a curved surface (21, 22), which reduces tilting of the semiconductor substrate (15), reduces temperature gradients across surfaces (23, 24) of the semiconductor substrate (15), and improves the reliability of the semiconductor diode device (10). The two heatsinks (11, 12) also include protrusions (19, 20), which help to keep the packaging material (16) covering the curved surfaces (21, 22) of the heatsinks (11, 12).

Abstract: A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.

Abstract: An electronic component includes a substrate (11) having a device surface (13) and opposite ends (14, 15) adjacent to the device surface (13), an electronic device (16) supported by the device surface (13), and an interconnect substrate (30) overlying a first end (14) of the substrate (11) and electrically coupled to the electronic device (16). The electronic component can be manufactured by inserting the second end (15) of the substrate (11) into one of a plurality of holes (23) in a carrier (20) wherein the device surface (13) and the carrier (20) form an angle greater than approximately five degrees.

Abstract: A flip-chip structure and method connects a semiconductor chip (11) having conductive bumps (16) to a substrate (12) having vias (19) extending from a first side (21) to a second side (18) of the substrate (12). A filler material (22) is deposited into the vias (19), and the conductive bumps (16) are inserted into the vias (19) for connecting the semiconductor chip (11) to a conductive element (17) covering the vias (19) on the second side (18) of the substrate (12).

Abstract: An electronic component has a body (11) that is formed from a mold compound that includes a thermoplastic material (31), a first filler (32) comprised of an electrically insulative material wherein the first filler (32) is more thermally conductive than the thermoplastic material (31), and a second filler (33) comprised of an electrically conductive material wherein the second filler (33) is more thermally conductive than the thermoplastic material (31).

Abstract: An etch stop layer prevents damage to the underlying semiconductor material or metallization layer during etching of a dielectric layer overlying the etch stop layer. The etch stop layer, aluminum nitride or aluminum oxide is used underlying silicon dioxide to prevent damage to the semiconductor material during a fluorocarbon based etch of the silicon dioxide. The etch stop layer is also used underlying a silicon dioxide layer and overlying a titanium nitride or titanium tungsten layer used in metallization to prevent etching of the titanium nitride or titanium tungsten layer during etching of the silicon dioxide.

Abstract: An apparatus for testing electronic devices in hostile media includes an isolation tank (24) which contains an inert or relatively inert material (26) such as fluorinated hydrocarbon liquid. Within the isolation tank (24) submersed in the inert or relatively inert material (26), is at least one test chamber (12) containing hostile and/or volatile test medium (14) such as a fuel mixture. Adjacent to the test chamber (12) and also within isolation tank (24) is a loading chamber (30) via which electronic devices to be tested are coupled to the test tank (12). The loading chamber (30), test tank (12) and isolation tank (24) are all isolated from the ambient environment and are oxygen free because they each contain a gas purge lines (33,35,38) providing an inert or relatively inert gas to a positive pressure within the respective tanks and chamber.

Abstract: An apparatus for and method of holding a semiconductor wafer (11) during a manufacturing process supports the semiconductor wafer (11) in a substantially planar form (15) with a two-platform wafer chuck (19). The two-platform wafer chuck (19) is compatible with handling warped and unwarped wafers, wafer transferring and handling techniques which maintain wafer flatness, and semiconductor manufacturing processes such as photolithography and auto-probing which require semiconductor wafers to be held in a flat configuration.

Abstract: A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.

Abstract: A sensor (10) includes a gate electrode (20) overlying a channel region (34). A gap (22) between the gate electrode (20) and the channel region (34) allows a surface (28) of the gate electrode (20) to be exposed to a chemical. Upon exposure to the chemical, a surface potential or an electrical impedance of the gate electrode (20) may change. Comparing the changes in surface potential versus the changes in electrical impedance provides a method to distinguish between similar chemical species and also to extend the detection range of the sensor (10).

Abstract: A method of forming an electrically conductive polymer bump (22) over an aluminum electrode (21) produces low contact resistance for an interconnect structure (24). Aluminum oxide is first removed from the aluminum electrode (21). Tiron and palladium are subsequently bonded to the fresh surface of the aluminum electrode (21). Finally, the electrically conductive polymer bump (22) is formed over the aluminum electrode (21). The Tiron and palladium improve the electrical contact between the conductive polymer bump (22) and the aluminum electrode (21) thereby reducing the contact resistance. The Tiron also inhibits corrosion of the aluminum electrode (21) and enhances the conductivity by catalytically shrinking the cyanate ester conductive bump.

Abstract: A method of fabricating an integrated circuit (272) having memory, logic, high voltage, and high current functionality uses a modular implant process step (104) to form a drain extension region (204), a source extension region (205), and a base extension region (206) in a substrate (200). The dopants from the modular implant process step (104) are later diffused into the substrate (200) during a LOCOS process step (105). A modular gate oxide formation step (111) produces three different thicknesses of gate oxides (309, 311, 312) which provide ultra high voltage, high voltage, and low voltage functionality for the integrated circuit (272).

Abstract: A system for locating electrically conductive features such as device terminals (104) of a semiconductor die device under test (103) includes an array of test terminals (101), an anisotropically conductive material (102) above the array of test terminals (101), and a semiconductor die (103). The array of test terminals has a pitch (203) much smaller than the pitch (204) of the device terminals (104). Individual test terminals (105) of the array of test terminals (101) are scanned to locate the device terminals (104). Once the device terminals (104) are located, the test terminals (105) are configured to send and receive functional signals required for functionally testing the device under test (103).

Abstract: A self-aligned semiconductor component (10) includes a layer (14) having two openings (36, 38) and overlying a doped region (13) in a substrate (11). One (36) of the two openings (36, 38) is used to self-align a different doped region (22) and a portion (27) of an electrode (27, 31). The electrode (27, 31) has another portion (31) overlying the self-aligned portion (27) to increase the current carrying capacity of the electrode (27, 31). A different electrode is formed in the other one (38) of the two openings (36, 38) and has a smaller current carrying capacity than the other electrode (27, 31).

Abstract: A method of defining a line width includes forming a spacer (45) over a layer (42) and using the spacer (45) as an etch mask (57) while etching the layer (42). In this manner, a width (47) of the spacer (45) is used to define a width or line width (47) for the layer (42). Another method of using a spacer to define a line width includes forming a spacer (14) over a substrate (11), depositing a layer (15) over the substrate (11) and the spacer (14), planarizing the layer (15) to expose the spacer (14), and removing the spacer (14) to form an opening (19) over the substrate (11), wherein the opening (19) has a width or line width (17) of the spacer (14).

Abstract: A method of packaging an electronic component includes forming a hole (24) in a substrate (21) having a first surface (22) opposite a second surface (23) and disposing and patterning a malleable layer (26) over the first surface (22) and over the hole (24) of the substrate (21). The malleable layer (26) has a third surface (27) opposite a fourth surface (28). A portion (29) of the fourth surface (28) is exposed by the hole (24) in the substrate (21). An electrically conductive layer is simultaneously disposed over the portion (29) of the fourth surface (28) and over a different portion of the third surface (27) of the malleable layer (26). The malleable layer (26) is deformed into the hole (24). Then, a semiconductor die (43) is coupled to the malleable layer (26), and an underencapsulant (37) is disposed under the semiconductor die (43) and over the hole (24).

Abstract: A light transmitting structure or optical waveguide (47) of the present invention can provide both optical and electrical conductivity. The optical waveguide (47) is capable of simultaneously transmitting multiple optical and electrical signals. The optical waveguide (47) has several cladding layers (40, 41, 42, 43, 44) which optically isolate several different regions of waveguide core material (45, 46) through which the multiple optical signals are transmitted. To provide a compact structure, portions of the cladding layers (42, 43, 44) of the optical waveguide (47) are used as electrical conductors while the waveguide core material (45, 46) is used as an electrical insulator for the electrical conductors.