Abstract: A method of adjusting a threshold voltage for a semiconductor device on a semiconductor on insulator substrate includes performing a threshold voltage adjustment implant (25) after formation of a gate structure (16) to reduce the diffusion of implanted dopant (26). Reducing dopant diffusion eliminates the narrow channel effect which degrades device performance. Implanting the dopant (26) after formation of the gate structure (16) simplifies processing of semiconductor device (28) by eliminating a photolithography step which is accomplished by utilizing photoresist (21) used for a source and drain implant (22).
Type:
Grant
Filed:
April 17, 1995
Date of Patent:
July 2, 1996
Assignee:
Motorola, Inc.
Inventors:
Marco Racanelli, Bor-Yuan C. Hwang, Juergen Foerstner, Wen-Ling M. Huang
Abstract: A method for enhancing aluminum nitride includes, in one version, annealing sputtered aluminum nitride in a reducing atmosphere (11), and subsequently annealing the sputtered aluminum nitride in an inert atmosphere (12). A superior aluminum nitride thin film (13) results. The films can withstand exposure to boiling water for times up to twenty minutes and maintain a refractive index, N.sub.f, greater than 2.0, and a preferred crystalline orientation ratio, I(002)/I(102), in excess of 1000.
Type:
Grant
Filed:
July 25, 1994
Date of Patent:
May 28, 1996
Assignee:
Motorola, Inc.
Inventors:
Keenan L. Evans, Hang M. Liaw, Jong-Kai Lin
Abstract: A semiconductor device having improved heat dissipating capability is provided. The preferred device in accordance with the invention includes an electronic device (12) formed in a surface (14) of a semiconductor die (10). The surface (14) is covered with a layer of diamond (20). Openings (24) are provided in the diamond layer (20) for access to the electronic device. A metallized pad (26) is provided on top of the diamond layer (20). Additionally, solder bumps (28) pass through the openings (24) in the diamond layer (20). A die attach substrate (32) is attached to the metallized pad (26) and the bumps (28). Heat is dissipated uniformly across the diamond layer (20) and is drawn off the device through the metallized pad (26). Electrical connections are made to the device via the solder bumps (28).
Abstract: A method for making a self-aligned oxide gate cap is provided. The method requires only one photoresist step to make a self-aligned oxide cap that can serve as an implant block and provide self-aligned contacts. A substrate with a gate line is provided. A first oxide layer (36) is then isotropically deposited over the gate line. A portion of the first oxide layer (36) is then etched anisotropically. A second oxide layer (40) is then isotropically deposited over the gate line and the remaining first oxide layer (36). A spacer mask (43) is then formed over the gate line. If preferred, the spacer mask (43) could be extended beyond the spacer region to further separate the drain region from the gate line with dielectric creating a lightly doped drain region. The exposed oxide layer is etched anisotropically, resulting in a dual-step spacer (44) that can act as an implant mask for the source and drain regions and as a self aligned ohmic contact area.