Abstract: An insulated gate semiconductor device (10) is fabricated by providing at least one ballast resistor (40) having a sheet resistance of at least one square. The ballast resistor (40) is formed in the emitter region (17) between two adjacent portions of the base region (26) at the top surface of the semiconductor body in which the device (10) is fabricated. The ballast resistor (40) improves the latch resistance of the device (10) in overload conditions.

Abstract: A transformer mount (11) supports a transformer (12) over a component (22) on a substrate (23) of a hybrid module (10). The transformer mount (11) conserves space in the hybrid module (10), improves high frequency performance by minimizing parasitic capacitances and inductances of the transformer mount (11), is compatible with subsequent high temperature and batch processing for faster assembly, permits the flow of defluxing materials beneath the transformer mount (11), is inexpensive, and provides appropriate access to fine tune the transformer (12) during assembly.

Abstract: A method is provided for reducing corrosion in openings on a semiconductor wafer. An etched opening is provided in a dielectric material on the semiconductor wafer. The etched opening and the dielectric material are cleaned with a basic solution. The exposed metal surface is treated with a hydrogen peroxide solution before exposing the exposed metal surface to an aqueous solution.

Abstract: A bipolar transistor (10) includes a collector region (13), a base region (14) in the collector region (13), and an emitter region (20) in the base region (14). A portion (18) of an electrical conductor (16) is located over a base width (23) of the bipolar transistor (10). The emitter region (20) is self-aligned to the portion (18) of the electrical conductor (16) and is preferably diffused into the base region (14) in order to decrease the base width (23) without relying on extremely precise alignment between base region (14) and the portion (18) of the electrical conductor (16). The portion (18) of the electrical conductor (16) is used to deplete a portion of the base width (23) of the bipolar transistor (10).

Abstract: A method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47) between the interconnect lines (11, 24, 26). Deposited over the interconnect lines (11, 24, 26), a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps (17, 47). Prior to the deposition of the sputter etched silane oxide layer (14), spacers (13, 42, 43) can be formed around the interconnect lines (11, 24, 26) to increase the aspect ratio of gaps (23, 31) between the interconnect lines (11, 24, 26) which facilitates the formation of the "breadloaf" shape of the silane oxide layer (14).

Abstract: A method of fabricating an optical waveguide (10) includes using an electrical discharge machine (20) to fabricate mold plates (41, 61) for molding cladding layers (11, 12) of the optical waveguide (10). The cladding layers (11, 12) contain rounded edges (15, 16) which are aligned to form a cylindrical channel or core (13). The cylindrical shape of the channel (13) improves the reliability of the waveguide (10) compared to waveguides having a conventional square or rectangular channel with sharp corners. An optically transparent material (17) fills the cylindrical channel (13) and serves as the medium through which light is transmitted. The refractive index of the optically transparent material (17) is greater than that of the cladding layers (11, 12) to keep the light within the cylindrical channel. The optically transparent material (17) also serves as an adhesive for the cladding layers (11, 12).

Abstract: A pressure sensor (11) and its method of fabrication include etching a V-groove (19) in a first surface (16) of a first substrate (12), bonding a second substrate (24) to the first substrate (12), thinning the second substrate (24) to form a diaphragm (32) overlying the V-groove (19), and etching a port (38) from the second surface (18) of the first substrate (12) to the V-groove (19). Tetra-methyl-ammonium-hydroxide is preferably used to anisotropically etch the V-groove (19), and an anisotropic plasma reactive ion etch is preferably used to etch the port (38).

Abstract: A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).

Abstract: A non-venting hazardous material liquid dispensing system (25) includes a removable supply vessel (7) coupled to a gas source (1) and a permanent buffer vessel (11). The permanent buffer vessel (11) is additionally coupled through a suction pump (14) to the removable supply vessel (7). The suction pump (14) suctions pressure off the permanent supply vessel (11), transferring the pressure to removable supply vessel (7). The transfer of pressure causes hazardous material liquid (34) to be drawn from the removable supply vessel (7) into permanent buffer vessel (11). The permanent buffer vessel (11) dispenses hazardous material liquid (34) to a process tool.

Abstract: A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

Abstract: Converting a Coriolis force into an electrical signal, an electro-mechanical transducer (10) is a field effect transistor (18) having angular velocity sensing capabilities. A gate electrode (16) is suspended over a channel region (60) of a substrate (31), is biased at a desired potential, and is oscillated along an axis (40). The gate electrode (16) and the substrate (31) are rotated about a different axis (41) at an angular velocity (44). The resulting Coriolis force displaces the suspended gate electrode (16) along yet another axis (42) which modulates a current (53) in the channel region (60) of the substrate (31). The amplitude of the current (53) describes the magnitude of the angular velocity (44).

Abstract: An edge die bond semiconductor package including a semiconductor die having an active major surface and a mounting edge substantially orthogonal to the active surface, a base having a mounting surface, and material affixing the mounting edge of the semiconductor die to the mounting surface of the base.

Abstract: A method of forming an alloyed drain field effect transistor (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A surface mount package (10) includes a leadframe (14) facing away from the mounting surface such that the primary heat path is away from the mounting surface. The package may be a modified TO-220, wherein the tab (16) of the leadframe is bent down toward the mounting surface, and the leads (20) are bent down and under the package. Such an embodiment provides for a small footprint and is relatively easy to manufacture.

Abstract: A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Abstract: An apparatus for and method of determining the coplanarity of leads of a semiconductor device is provided. The apparatus comprises a base (24) for placing the semiconductor device, and a plurality of mirrors (38) and (36) surrounding the base. The mirrors reflect an image of the leads of the semiconductor device to a camera. The camera records an image from which the lead coplanarity is determined. The base contains an optical datum (34) which provides a reference plane from which to measure coplanarity. The mirrors can be placed such that an off-axis image of the leads is reflected to the camera. The off-axis image improves the apparent sensitivity of the coplanarity measurement.

Abstract: A system and method for aligning a semiconductor device (10) to a fixture (11) is provided. A first physical alignment feature (12) on the semiconductor device (10) and a second physical alignment (24) on the fixture (11) mate to align and hold the semiconductor device (10) in place. In one embodiment the physical alignment features (12) and (24) are produced using standard photolithography techniques, resulting in precise alignment features. In another embodiment the physical alignment features (12) and (24) are designed and placed to control the direction the thermal expansion of the semiconductor device (10) relative to the fixture (11).

Abstract: An optocoupler package (40) has two pre-molded thermoplastic halves (42, 54); one containing the emitter (16) and the other containing the detector (18). The detector half (54) has a well (56) where the detector (54) is located. The well (56) is filled with silicon die coat gel (24). The emitter half (42) has a similar well (48) containing the emitter. Surrounding the well (48) of the emitter half is a protruding wall (50) with relief vents (52). The wall (50) is configured to fit into the perimeter of the well (56) of the detector package half (54). When the package (40) is assembled, the protruding wall (50) of the emitter half (42) is inserted into the well (56) of the detector package half (54), thereby displacing the gel (24) so as to completely fill the internal chamber (66) and spill into the relief vents (52).

Abstract: A system for locating electrically conductive features such as device terminals (104) of a semiconductor die device under test (103) includes an array of test terminals (101), an anisotropically conductive material (102) above the array of test terminals (101), and a semiconductor die (103). The array of test terminals has a pitch (203) much smaller than the pitch (204) of the device terminals (104). Individual test terminals (105) of the array of test terminals (101) are scanned to locate the device terminals (104). Once the device terminals (104) are located, the test terminals (105) are configured to send and receive functional signals required for functionally testing the device under test (103).

Abstract: Flip chip bumps (24, 26, and 27) and an inductor (17) are simultaneously fabricated on a semiconductor substrate (10). The fabrication process includes two electroplating steps. The first step electroplates copper (18) onto a seed layer (13) to form the inductor (17) and a first portion (16) of the flip chip bumps (24, 26, and 27). The second step electroplates copper (21) onto the previously electroplated copper (18) to form a second portion (21) of the flip chip bumps (24, 26, and 27).