Patents Represented by Attorney, Agent or Law Firm Jiawei Huang
  • Patent number: 8020301
    Abstract: A method for manufacturing a hydro dynamic bearing device is provided for the finishing treatment of lubricating oil after lubricating the hydro dynamic bearing device, specifically for properly and effectively wiping off the lubricating oil adhering to the outside of the housing and adjusting the oil-level height of the lubricating oil filled in the housing.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: September 20, 2011
    Assignee: NTN Corporation
    Inventors: Masayuki Kaimi, Kazuto Shimizu, Kimihiko Bitou, Nao Ishiyama, Nobuyoshi Yamashita
  • Patent number: 7549459
    Abstract: A crystallizer and method for casting using the crystallizer. The crystallizer mainly includes a plurality of-position-limiting parts (16) on the inner side of the mould seat (6, 7). The inner side of the position-limiting parts (16) is in correspondence with the external periphery of the mould wall (8-1, 9-1) of the film mould (8, 9). A medium channel (17) with a medium-supplying port (5) at its upper end is formed between the adjacent position-limiting parts (16).
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: June 23, 2009
    Assignee: Beijing TaiHe Technology Co., Ltd
    Inventor: Jingen Sun
  • Patent number: 6723371
    Abstract: As embodied and broadly described herein, the invention provides an electrode test strip. The electrochemical electrode test strip comprises an insulating base plate, a electrode system on the base plate, a spacer which partially covers the electrode system and a channel trench with a constant width is formed thereof, a reactive film, and a cover on the spacer with an first opening thereof. Wherein the electrode system comprises at least a working electrode and a reference electrode, and the working electrode and the reference electrode is isolated. The reactive film contains at least on active species that can have a specific redox reaction with the analyte. The first opening exposes the channel trench, and two second openings are located at the two ends of the channel trench.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 20, 2004
    Assignee: Bioptik Technology, Inc.
    Inventor: Lee Chih-hui
  • Patent number: 6609846
    Abstract: A writing instrument with a retractable refill mechanism comprises: an replaceable refill having a front end as the pen tip, a pen barrel which has a front end opening and accommodates said refill, a slider positioned at the rear end of the refill and slidable in the cavity inside of said pen barrel, a connecting rod with one end pivotally connected to said slider, an inner gear mounted inside of the pen barrel and off-axially and pivotally connected with said connecting rod, and an outer gear mounted inside of the pen barrel and engageable with said inner gear. Therefore, by means of the connecting rod off-axially connected to the rotatable inner gear, the rotation of the inner gear is converted to a linear motion of the slider.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: August 26, 2003
    Assignee: Longreen Marketing Ltd.
    Inventors: Kui-Cheung Lai, Shun Sang Poon
  • Patent number: 6610914
    Abstract: A sonic-vibration-generating mechanism of a piano is divided into a two-segment structure made up of the sonic-vibration-generating mechanism of the upstream side A and the sonic-vibration-generating mechanism of the downstream side B, and the sonic-vibration-generating mechanism of the downstream side is placed in a layered state onto the sonic-vibration-generating mechanism of the upstream side, with a plural number of weight-supporting elements of a point-support type or a line-support type allocated in between in rows at certain uniform intervals on the support frame 19 installed in the sonic-vibration-generating mechanism of the upstream side A.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: August 26, 2003
    Inventor: Ueno Yasunaga
  • Patent number: 6606819
    Abstract: Organic media are derived from natural organic materials, which are coconut dust, simple coconut dust, or those containing coconut staple fibers, coconut pericarp chips, and are beaten bark, which is both broadleaf trees and needleleaf trees, and sawdust. These natural organic materials contain a lot of organic acids and salt (NaCl). The feature of the present invention is treatment using the modifying reagents to eliminate the organic acids and salt that adversely affect the cultivation of plants. The modifying reagents consist of at least one salt selected from among iron salts and aluminum salts, and the modified organic media obtained by modifying the natural organic materials with the modifying reagents. The natural organic materials are preferably coconut dusts, beaten bark, and sawdust. The modifying materials of 0.1 to 5 g is preferably applied to the natural organic materials of 100 g in dry weight.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: August 19, 2003
    Assignee: Createrra Inc.
    Inventor: Tomotaka Yanagita
  • Patent number: 6579560
    Abstract: A soybean processed food having crisp feelings of eating and good tasting is provided. The soybean processed food is produced by kneading a mixture of a soybean-derived material and a condiment in the presence of water to obtain dough, and drying the dough under a reduced pressure of 0.1 kPa to 10 kPa. It is preferred that the soybean-derived material contains isolated soybean protein as the major constituent, soybean saccharide, soybean dietary fiber, and/or soybean lecithin.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: June 17, 2003
    Assignee: Sanko Corporation
    Inventors: Masaru Kagawa, Koichiro Shioaki, Rumi Tsuchiya, Noriaki Hayashi, Takahiko Mitani
  • Patent number: 6544456
    Abstract: A method for the production of melt-spun fibers comprising polyethylene terephthalate as a fiber-forming polymer, through polycondensation or melting of the fiber-forming polymer forming a melt and subsequently melt spinning, comprises mixing 0.1-4 wt %, relative to the fiber-forming polymer, of polymethyl methacrylate with the fiber-forming polymer before the melt spinning and dispersing the polymethyl methacrylate in the fiber-forming polymer to form unoriented melt fibers. During the melt spinning, the spinning speed of the fibers is set at up to 8000 m/min, whereby through the inclusion in the unoriented melt fibers, extruded from a sincerest, rod-shaped inclusions of the polymethyl methacrylate with a lateral particle size of less than 800 nm are obtained.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: April 8, 2003
    Assignee: Inventa-Fischer AG
    Inventors: Raimund Schwarz, Werner Stibal, Gustav Schütze
  • Patent number: 6478205
    Abstract: A portable telephone set holder is comprised of a portable telephone set housing, a holding section extending from the housing, and a suspending section provided on a rear surface of the housing. The housing has an insertion port, into which a portable telephone set is inserted to be housed. The holding section extends from the insertion port and is provided at a location adjacent to the insertion port, which housing is folded toward a front surface of the housing, and engaged with the housing in a disengageable manner. The suspending section forms a supporter insertion block on the rear surface of the housing in a disengageable manner. A supporter such as a belt is inserted into the supporter insertion block, to thereby suspend the portable telephone set holder. The opening surface of the insertion port of the housing is inclined in one orientation. Further, the supporter insertion block is inclined in the same orientation as the inclined orientation of the opening surface.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: November 12, 2002
    Inventor: Kouichiro Fujihashi
  • Patent number: 6441905
    Abstract: There is provided a sheet thickness and swell measurement method and apparatus to calibrate a characteristic map of a reference plane with accuracy and on demand, and to provide a simpler construction of means for creating the characteristic map of the reference plane and means for calibrating the characteristic map. Measurement heads 2 are moved to the width direction of sheet 9, and the thickness of the sheet is measured by the sheet thickness measurement sensors 3 installed in the measurement heads 2. The measured values of the sheet thickness are calibrated by a characteristic map MP of the moving mechanism 4 of the measurement head 2 with respect to the sheet width direction, which has been created in advance. Highly directional electromagnetic waves emitting means is arranged on one side of the main frame 1 for emitting highly directional electromagnetic waves 5a, such as light or beam, which define a reference plane for creating the characteristic map.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: August 27, 2002
    Assignee: Yamabun Electric Co., LTD
    Inventors: Fumjo Tojyo, Shunzo Hirakawa
  • Patent number: 6425606
    Abstract: A diffractive anti-counterfeiting tag structure with capabilities of naked-eye inspection and machine inspection and its method of manufacture. The anti-counterfeiting tag structure has a naked-eye inspection component and a machine inspection non-grating diffractive component. The naked-eye inspection component and the non-grating diffractive component are formed on separate mold-boards and then joined together to form a mold-board using a board-joining technique. Alternatively, a plurality of naked-eye inspection blocks and a plurality of non-grating diffractive blocks are randomly mixed together to form a pixel-like diffractive anti-counterfeiting tag.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: July 30, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Ying-Tsung Lu, Jeng-Feng Lin, Pong Lai, Pai-Ping Huang, Wann-Diing Tyan, Hoang-Yan Lin
  • Patent number: 6415974
    Abstract: A structure of solder bumps with improved coplanarility, comprising a substrate, a passivation layer, a plurality of Under Ball Metallurgy (UBM) layers and a plurality of solder bumps. The substrate has at least an active surface, and a plurality of bonding pads are provided thereon. The UBM layers with various areas are electrically connected to the bonding pads. Finally, the solder bumps are formed with uniform-height on the UBM layers. A method of forming solder bumps with improved coplanarity. A UBM structure with various sizes of openings is provided to control the volume of the solder, wherein the various sizes of openings are corresponding to the current distribution across the wafer. The purpose of the various openings is to control the volume of the solder in order to form uniform-heights of solder bumps, the coplanarity of the solder bumps can thus be improved.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: July 9, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Jui-Meng Jao
  • Patent number: 6415407
    Abstract: A debugging device is provided for use in a system controller chip on a computer motherboard, such as a Pentium-based computer motherboard, to facilitate a debugging procedure on the system controller chip whenever a malfunction occurs to the system controller chip. Consequently, internal signals of the chip are correctly connected to chip leads. Under normal operating conditions of the system controller chip, the debugging device connects the connecting-pad area to the control unit and disconnects the connecting-pad the control unit and connects the connecting-pad area successively in a predetermined sequence to the function blocks, allowing the function blocks to undergo an on-site debugging procedure one by one. The debugging device allows an on-site debugging procedure on the system controller chip in real time, and also allows the system controller chip to undergo a benchmark test to check for the reliability in the overall functionality of the system controller chip.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: July 2, 2002
    Assignee: Via Technologies, Inc.
    Inventor: Nai-Shung Chang
  • Patent number: 6412039
    Abstract: A cross memory bank, cross memory page data accessing and controlling unit that provides more efficient transfer of data between a CPU and a memory cluster is described. The data accessing and controlling unit comprises a CPU interface circuit and a memory controlling circuit. When the CPU submits consecutive data access requests to the CPU interface circuit for accessing memory, addresses of the requested data do not necessarily lie in the same memory bank or the same memory page of the memory cluster. If the requested data lie on a different page or a different bank, the CPU interface circuit sends out cross-bank or cross-page signals to the memory controlling circuit in addition to the internal data request signal. Therefore, the required page in the memory bank can be opened in advance. Consequently, time for memory access is shortened and overall efficiency of the system can be improved.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: June 25, 2002
    Assignee: Via Technologies, Inc.
    Inventor: Nai-Shung Chang
  • Patent number: 6403471
    Abstract: A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: June 11, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chine-Gie Lou
  • Patent number: 6399286
    Abstract: A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: June 4, 2002
    Assignee: Taiwan Semiconductor Manufacturing Corp.
    Inventors: Yuan-Hung Liu, Bor-Wen Chan
  • Patent number: 6391708
    Abstract: A method of manufacturing a DRAM capacitor comprises the steps of providing a semiconductor substrate having a source/drain region thereon, and then forming an insulating layer over the substrate. Next, a storage node opening that exposes the source/drain region is formed in the insulating layer, and then a conductive layer is formed above the storage node opening and the insulating layer. Thereafter, porous insulating material is deposited over the first conductive layer. The porous material includes porous oxide, NanoPorous Silica or Xerogel Sol-Gel, for example. Subsequently, the porous insulating layer is used as a mask to carry out a plasma-etching operation so that a portion of the conductive layer is etched away to form a plurality of long and narrow crevices. Hence, a fork-shaped conductive layer is formed. The fork-shaped first conductive layer serves as the lower electrode of a capacitor.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: May 21, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Kuan-Yang Liao
  • Patent number: 6372564
    Abstract: A method of manufacturing a V-shaped flash memory. The V-shaped stack gate is formed by implanting ions into a substrate to form a buried source line using a mask, and then forming a V-shaped trench that exposes the buried source line in the substrate. A V-shaped word line stack gate is next formed over the trench and the substrate next to the trench. A common drain terminal is formed in the substrate on each side of the V-shaped stack gate. The drain terminal is electrically connected to a bit line by forming a contact plug.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: April 16, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Robin Lee
  • Patent number: 6362048
    Abstract: A method for manufacturing the floating gate of a flash memory. First, a substrate is provided. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Gate position is defined and then the silicon nitride layer above the gate position is removed. Th exposed polysilicon layer is oxidized to from a floating gate oxide layer. A buffer layer is formed over the silicon nitride layer and the floating gate oxide layer. A first spacer is formed on the sidewall of the buffer layer. Thereafter, a second spacer is formed. Using the second spacer as a mask, the exposed floating gate oxide layer is removed. The buffer layer, the first spacer and the second spacer above the polysilicon layer and the floating gate oxide layer are removed. Finally, the polysilicon layer not covered by the floating gate oxide layer is removed to form a complete floating gate of a flash memory.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: March 26, 2002
    Assignee: Winbond Electronics Corp.
    Inventor: Shui-Chin Huang
  • Patent number: 6362662
    Abstract: A winner-take-all (WTA) circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal, to assist in the decision criteria of a winner-take-all network. The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current and a voltage level is outputted. The reference current is adjustable, and the invention also provides a WTA circuit with weighted inputs, and the ability to select between a 1-WTA, and a 2-WTA configuration. The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: March 26, 2002
    Assignee: Winbond Electronics Corp.
    Inventors: Bingxue Shi, Guoxing Li