Abstract: A method of fabricating a node contact opening is described. A dielectric layer is formed on a substrate. A first conductive layer is formed on the dielectric layer. The first conductive layer is etched to form a trapezoidally cross-sectioned opening exposing a portion of the dielectric layer. The dielectric layer exposed by the trapezoidally cross-sectioned opening is etched to form a node contact opening in the dielectric layer exposing a part the substrate. A second conductive layer is formed to fill the node contact opening and in contact with the conductive layer.

Abstract: A spindle motor is lifted up to an attachment position, and a yoke inside a disc clamp is then attracted by a circular ring magnet in a turntable on the spindle motor. When the spindle motor is lowered down, the magnetic conductive material is attracted by a circular ring magnetic on a chucking plate. Thus, the disc clamp is moved up-and-down automatically by means of magnetic attraction, and interference with a cartridge is prevented. By comparison with prior art disc clamping apparatus which utilizes a spring or lever mechanism, the present invention can reduce both an operating space and a number of components. Also, the complexities of design and assembly are reduced, and collisions between devices are avoided.

Abstract: A voice detection method and apparatus is provided, which can detect whether a received signal is a voice signal or a background noise. By the method and apparatus, the voice detection need not to perform multiplications and divisions. Moreover, the voice detection method and apparatus can encode the sampled data into 8-bit format but nonetheless obtain good detection result. Further, the voice detection method and apparatus can prevent overflow and allow for easy refreshing of the preset threshold of background noise. These benefits allow the hardware circuitry that implements the voice detection method and apparatus to be significantly simplified in complexity, and thus significantly reduced in manufacturing cost.

Abstract: A temperature sensing system for monitoring and controlling temperatures of various peripheral devices inside a notebook type of computer. The temperature sensing system uses a thermistor as a temperature sensor. The thermistor is positioned around a peripheral device and forms a potential divider circuit with another resistor. Next, the voltage produced by the divider circuit is fed to a voltage detection pin of a chipset. Inside the chipset, the divider voltage can be compared with a reference so that appropriate action can be taken to cool down a particular peripheral device. In addition, the temperature sensor of this invention can be placed anywhere inside a notebook computer including the area surrounding the peripheral device or even inside the peripheral device. Moreover, no additional control chips for operating those temperature sensors arc needed, and hence production cost can be lowered.

Abstract: A wide-range and low power consumption voltage-controlled oscillator according to the invention includes a logic control circuit, a parallel series controllable inverter bank and a voltage control load. The logic control circuit consists of a plurality of logic gates for receiving a selecting signal from an external device and then transmitting a control signal. The parallel series controllable inverter bank consists of a plurality of series controllable inverter banks electrically connected in parallel for receiving the control signal and outputting an oscillation signal, wherein the control signal is used to control the number of the series controllable inverter banks electrically connected in parallel. The voltage control load is electrically connected between the parallel series controllable inverter bank and ground for serving as a load of the parallel series controllable inverter bank.

Abstract: A method is used to fabricate an electrically erasable programmable read only memory. First, a substrate is provided. Then, a doped polysilicon pillar is formed on the substrate. Furthermore, a source is formed in the substrate beneath the doped polysilicon pillar. Finally, the other structures of the memory are completed in sequence.

Abstract: A metal-line structure in an integrated circuit (IC) and a method of fabricating the same are provided. The metal-line structure includes a barrier layer formed at a selected location over the dielectric layer, a metallization layer formed over the barrier layer, an ARC formed over the metallization layer, and a spacer structure formed over all the exposed sidewalls of the barrier layer, the metallization layer, and the ARC. The forming of the spacer structure on each of the metal lines can help prevent the occurrence of extrusions along the sidewalls of the metal lines in the IC device that would otherwise cause dielectric cracks and thus lead to undesired bridging between neighboring metal lines as in the prior art. Moreover, the method of fabricating such a metal-line structure can be carried out without having to perform photolithography, thus reducing manufacturing cost.

Abstract: A dynamic random access memory suitable for use as a compatible transistor of a static random access memory and the method for operating the same. A static random access memory with a single transistor is applied to effectively store the data saved in the dynamic random access memory without being lost. In addition, the dynamic random access memory can be operated under a low voltage to retain the data stored in the dynamic random access memory cell, and to reduce the power consumption. With the structure of such dynamic random access memory, the data stored in the dynamic random access memory can be retained under the stand-by mode, and the operation power consumption can be reduced.

Abstract: A device for chemical-mechanical polishing. The device can be applied to a chemical polishing table spinning in a fixed direction and a polishing pad above of it. A chemical-mechanical polishing device according to the present invention is at least comprised of a main body of conditioner with a plurality of mounting pads, wherein each mounting pad is mounted with the diamond granules and located on the lower surface of conditioner, distributed on the rim of main body of each mounting pad. It can contact with polishing pads when cleaning the polishing pads and a number of cavities are across the upper and lower surfaces of each main body of conditioner and distributed between each mounting pads as well. When using the conditioners to clean out the polishing pads, the de-ionized water will flow through the cavities to wash off the acid or basic slurry to eliminate the destruction made by the solders around the diamond granules to extend the durability of the conditioner.

Abstract: A method for high-density plasma etching. A substrate is provided. A material layer is formed on the substrate. A patterned photo-resist layer is formed on the oxide layer. The material layer is patterned by the high-density plasma etching, simultaneously, a formation of a barrier layer over the substrate with the patterning process is suppressed and nitrogen gas generated in the patterned photo-resist layer is reduced.

Abstract: A method of fabricating a contact window of a semiconductor device is described in which a conductive layer is used to cover the boundary of the neighboring isolation structure of the source/drain region, or to also cover the source/drain region. An insulation layer is formed on the entire substrate. The insulation layer is then defined to form a contact window, exposing the source/drain region or exposing the conductive layer located on top of the source/drain region.

Abstract: A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

Abstract: A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. An etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer and a wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.

Abstract: A method of fabricating bit lines is described. A semiconductor substrate has isolation structures formed therein. Gate structures are formed over the semiconductor substrate. Each gate structure comprises a conducting gate layer and a cap layer on the conducting gate layer. A common source and a drain is formed in the semiconductor substrate. A spacer is formed on the sidewall of each gate structure. A dielectric layer is formed over the semiconductor substrate. The dielectric layer is patterned to form bit line contact holes and bit line trenches, wherein the bit line contact holes expose the common sources, and the bit line trenches expose a part of the cap layer and a part of the isolation structures. The bit line contact holes and the bit line trenches are filled with a conducting layer; consequently, bit line contacts and patterned bit lines are formed.

Abstract: A method of fabricating a gate is described. A first dielectric layer having a first opening is formed on a substrate. A gate dielectric layer is formed in the opening. A lower portion of a floating gate is formed on the gate dielectric layer. A source/drain region is formed in the substrate beside the lower portion of the floating gate. A conductive layer is formed on the first dielectric layer to completely fill the first opening. The conductive layer is patterned to form a second opening in the conductive layer. The second opening is above the first opening and does not expose the first dielectric layer. The second opening has a tapered sidewall and a predetermined depth. A mask layer is formed to cover the conductive layer and fill the second opening. The mask layer outside the second opening is removed to expose the conductive layer. A portion of the mask layer is removed to leave a first etching mask layer in the second opening.

Abstract: A device and method for manufacturing an integrated real time clock integrated circuit (RTC IC) package is disclosed, in which the RTC IC and its related components are integrated into a single package. Therefore, the layout area required by the integrated RTC IC package is significantly reduced. Also, only a single manual assembling process is required. Furthermore, various examination steps are built into every process to manufacture the integrated RTC IC package to make sure the completed products are in normal condition. No extra examination and fix-up processes are required for the completed products so that manufacturing cost can be significantly reduced.

Abstract: A monitor control system capable of reprogramming the function of a monitor. The monitor control system utilizes VGA signal lines for video signal transmission during normal mode of operation and the same VGA signal lines for transmitting erase/record commands and data when the erasable programmable ROM inside the monitor demands reprogramming. Using an isolator circuit in the monitor control system for isolating an erase/record pathway of an erasable programmable ROM from a normal video pathway, data within the erasable programmable ROM can be modified without opening up the monitor casing. Hence, the modification of monitor function is much more convenient.

Abstract: A method of forming a flash memory device is described. A substrate at least comprises a memory region and a peripheral circuit region. A stacked gate is formed on the memory region. The stacked gate comprises a tunneling oxide layer, a floating gate and a control gate. A capacitor is formed on the peripheral circuit region. A dielectric layer is formed over the substrate to cover the peripheral circuit region. A thin spacer is formed on the sidewall of the stacked gate. A doped region is formed in the memory region by ion implantation. A thermal process is performed to drive the dopant in the doped region into the substrate and to oxidize a part of the floating gate above the edge of the tunneling oxide layer.

Abstract: A method for fabricating an SOI semiconductor device with reduced floating body effects and a simplified method of fabrication. In the invention, a N-type doped dielectric layer or P-type doped dielectric layer is used to be driven into the semiconductor layer to form source/drain regions of field effect transistors of CMOS and conductive regions. For fabricating a NMOS transistor and a PMOS transistor of the CMOS device, the invention provides a method which an ion implantation process and a photo mask are omitted, by which the method will decrease the complexity of the fabrication process and the cost thereof.

Abstract: A method of manufacturing a crown-shaped DRAM capacitor. A silicon oxide layer and a silicon nitride layer are sequentially formed over a substrate. A conductive plug passing through the silicon oxide layer and the silicon nitride layer is formed. A first and a second dielectric layer are sequentially formed over the silicon nitride layer and the conductive plug. A first opening that exposes the conductive plug and a portion of the silicon nitride layer surrounding the plug is formed in the second and the first dielectric layer. A doped amorphous silicon layer conformal to the substrate profile is formed. The doped amorphous silicon layer above the second dielectric layer is removed. The second dielectric layer is next removed, and then hemispherical silicon grains (HSGs) are grown over the exposed surface of the doped amorphous silicon layer. The first dielectric layer is removed, and finally a third dielectric layer and a conductive layer are sequentially formed over the substrate.