Abstract: A twisted nematic color liquid crystal display. The liquid crystal display comprises parallel glass substrates covered by a transparent electrode and an alignment film, a twisted nematic liquid crystal between the glass substrates, a retardation layer and polarizers. Between the glass substrates, a liquid crystal unit which forms the liquid crystal has a twist angle about 70 to about 180 about degree while free of an externally applying voltage. A product of anisotropy of refractive index for the twisted nematic liquid crystal &Dgr;n and the thickness d thereof, that is, &Dgr;n·d, is set in a range between about 1100 Å to about 2000 Å. Without using a passive device such as an external color light source or color filter, a multi-color or full color display is formed by an active controlling method of birefringence of electric field via applying a voltage on the transparent electrode.

Abstract: A flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

Abstract: A method for manufacturing a diffusion barrier layer over a substrate having a patterned copper layer. A refractory metal layer or a nitride layer of refractor metal is formed on the substrate and a top surface and a sidewall of the patterned copper layer. The refractory metal layer or the nitride layer of refractor metal is converted by HDP treatment into an implanted layer as a diffusion barrier layer, where gas of N2, O2, NH3, NO2; or N2O are used for producing implanting ions. A thermal process is performed stabilize a diffusion barrier quality of the oxygen-containing implantation layer.

Abstract: A method for recovering the alignment mark on a substrate to the top of a dielectric layer. The method includes the steps of forming a dielectric layer over a substrate, and then forming a cap layer over the dielectric layer. The cap layer fills the trench in the dielectric layer directly above the alignment mark and covers the area surrounding the trench. Thereafter, a global planarization is carried out to remove the top portion of the cap layer. Finally, the remaining portion of the cap layer is removed to expose the dielectric layer so that an alignment mark re-emerges on top of the dielectric layer.

Abstract: A alarm system for waste liquid discharge blockage for early warning when blockage results from waste liquid. In the blockage alarm system for waste liquid discharge according to the present invention, the discharge line connected to the outlet of waste liquid of the machine is arranged such that the discharge line is angled in the ranges of about 185 to 265 degrees to allow the waste liquid flow smoothly. The first pipe and the second pipe of the sensing line are arranged roughly under the connection of the discharge line and the lowest outlet, and located to make the angle between the first pipe and the discharge line of the sensing region in the range of about 95 to 175 degrees and the angle between the second pipe and the discharge line of the sensing region in the range of about 95 to 175 degrees when the discharge line of the sensing region is vertical. The flow back of the waste liquid into the sensing region can be inhibited. A sensor can be provided in the sensing line for detection of blockage.

Abstract: A pre-charged high-speed comparator includes a first negative phase logic switch, a second negative phase logic switch, a third negative phase logic switch, a first positive phase logic switch, a fourth negative phase logic switch, a second positive phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch and a fifth positive phase logic switch. The two output terminals of the pre-charged high-speed comparator is raised to a voltage roughly half of a source voltage so that the time required for a regeneration circuit that includes the third negative phase logic switch, the first positive phase logic switch, the fourth negative phase logic switch and the second positive phase logic switch to get into the transistor active region is shortened, thereby increasing the overall operating speed of the comparator circuit.

Abstract: A method of fabricating a dual damascene structure. The method forms a silicon oxide layer, a stop layer, a low k organic dielectric layer, and a cap layer are formed in sequence on a substrate. A trench is formed in the cap layer and the low k organic dielectric layer, while a via opening is formed in the stop layer and the silicon oxide layer. A part of the stop layer is removed to form a cavity below the low k organic dielectric layer, followed by forming fluorinated poly-arlyethers spacers on sidewalls of the trench and the via opening which fills the cavity. The trench and the via opening are then filled with a copper layer to form a dual damascene structure.

Abstract: A fabrication method for an electrically erasable programmable read only memory is described in which the memory cell has a sharp-cornered polysilicon pillar in junction with the source region to enhance the source side Fowler-Nordheim tunneling effect. The fabrication method sequentially forms an oxide layer and a silicon nitride on a silicon substrate, and then patterns the oxide layer and the silicon nitride layer to form a plurality of trenches. A first doped polysilicon layer is then formed on the substrate and fills the trenches. A wet oxidation is then conducted to grow an oxide layer on the first doped polysilicon layer, from which a sharp-cornered doped polysilicon layer results. A first dielectric layer is further formed on the substrate and the doped polysilicon layer, followed by forming a floating gate on the first dielectric layer. After this, a second dielectric layer is formed on the substrate, covering the floating gate, and a control gate is formed on the second dielectric layer.

Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.

Abstract: A method of fabricating a via plug for self-aligned interconnects is provided. The method features initially forming a polysilicon buffer layer and a silicon oxide layer in sequence on an inter-polysilicon dielectric (IPD) layer, followed by forming a trench opening in the silicon oxide layer. The trench opening is then filled with a metal line. A patterned photoresist layer is formed on the silicon oxide layer to form a photoresist opening which exposes a part of the metal line. The exposed part of the metal line and a part of the polysilicon buffer layer are removed to expose a part of the IPD layer, followed by removing the photoresist layer and the silicon oxide layer. With the polysilicon buffer layer and the metal line serving as a mask, the exposed part of the IPD layer is removed to form a via opening. The via opening is then filled with a polysilicon layer which is formed on the polysilicon buffer layer and the metal line.

Abstract: A fabrication method for a gate structure formed on a substrate, which has isolation structures formed therein. A buffer oxide layer is formed, followed by forming a patterned nitride layer and a patterned mask layer. The patterned nitride layer and the patterned mask layer defines a gate opening for forming a gate stack comprising a gate oxide layer, a doped polysilicon layer, a metal silicide layer, and a cap layer. Consequently, a source/drain region is formed through performing a LDD implantation, while a spacer is formed on a sidewall of the gate stack to complete the manufacture of a gate structure.

Abstract: A crack-preventive substrate for fabricating a solder mask in a device site region includes a substrate, which has a top surface and a bottom surface, and a solder mask layer. The substrate is divided into a device site region and a periphery region. The solder mask layer, disposed on the top surface and bottom surface of the substrate, forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. And the bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”. As a result, the crack lines generated on the solder mask layer at the perimeter of the substrate will not develop toward the solder mask in the device site region.

Abstract: A method of fabricating a semiconductor device is described in which an insulation layer is formed over the gate electrode and the substrate. This insulation layer is anisotropically etched away except for a portion surrounding the sidewall of the gate electrode to form a spacer. The tip of the spacer is at the same height as the upper surface of the liner layer and is lower than the upper surface of the gate electrode, therefore, resulting in an increase of the exposed area of the gate electrode surface.

Abstract: A packaging process and structure of electronic device provides first a substrate having a carrying surface and a mounting surface wherein the carrying surface is divided into a device disposing region and a device peripheral region. Then a hydrophobic Fluorine-containing layer is formed in the device peripheral region of the substrate. Subsequently, an electronic device is attached in the device disposing region and is electrically connected to the substrate. Then, a molding compound is employed to encapsulate the electronic device. The bondability between the hydrophobic Fluorine-containing layer and the molding compound is weaker than the bondability between the molding compound and the substrate. Finally, a degating process is performed to remove the excess molding compound positioned at the hydrophobic Fluorine-containing layer to accomplish the packaging process of the electronic device.

Abstract: A method is provided for use on an OSD-based (On-Screen Display) video display system, such as a VCD system, a super VCD system, or a DVD system, for the purpose of enhancing the resolution of cursor movement on the display screen of the video 5 display system. This method can help achieve the cursor movement resolution enhancement simply through software modifications without having to modify or add extra hardware to the existing video display system. By this method, the OSD blocks are partitioned into an array of subblocks, one subblock representing one resolution unit for the cursor movement. A number of predesigned sets of fragmented cursor patterns are provided and prestored in the display memory of the video display system. A corresponding set of fragmented cursor patterns can be retrieved for display in specified OSD blocks in response to a particular movement of the cursor over the display screen.

Abstract: A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg.

Abstract: A polygonal ratchet wrench with an illuminating device including a hollow housing and a matching body is characterized on that: the hollow housing has interior positive leads, negative leads and batteries for forming a complete power supply unit, and lamps for illuminating the working area as well as the object therein are constructed at a bottom of the matching body and the bottom of the hollow housing. By providing a receiving hole of the matching body, a labor-saving extension bar can be engaged for extending the force arm of the polygonal ratchet wrench.

Abstract: A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.

Abstract: A device installed in a computer system for protecting the program or data inside a programmable non-volatile memory. The device includes a first and a second combinatorial logic circuit, a delay circuit, a low-enable latching device with reset capability, an AND gate and a memory cell array. As soon as all the necessary system startup operations dictated by the BIOS program inside the memory cell array are executed and a specified memory read/write program that matches the preset internal parameters of a logic circuit is activated so that output from the AND gate is a logic ‘false’, the memory cell array is permanently locked in a non-programmable state, unless the power is turned off and then restarted again. There is no way for any software program to change the programming state of the memory cell array back to a re-programming state again. Hence, the device is an effective means of protecting the programs inside the memory from illegal tampering.

Abstract: A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C49 phase into a low-resistance C54 phase.