Abstract: A pseudo bipolar junction transistor according to the invention includes two MOS transistors operating in saturation region, electrically connected in parallel with their drains and sources functioning as a collector and a emitter of the pseudo bipolar junction transistor, respectively, a first gate without any signal inputted and a second gate functioning as a base of the pseudo bipolar junction transistor, wherein the two gates is supplied with the same DC bias. The pseudo bipolar junction transistor is manufactured by CMOS process for applications in variable gain amplifiers, transfer linear function signal processors and logarithmic filters.

Abstract: A random access memory cell. The RAM cell includes a first transistor and a second transistor. A control gate of the first transistor is coupled to a control signal line. A data read terminal of the first transistor is coupled to a data read line. An earth terminal of the first transistor is connected to a ground. A floating gate terminal of the first transistor is located between a portion of a substrate and a portion of the control gate. A control gate of the second transistor is also coupled to the control signal line. The data write terminal of the second transistor is a data write line. A data transmission terminal of the second transistor is coupled to the floating gate of the first transistor. To write data into the RAM cell, a write control voltage is applied to the control signal line. Similarly, to read data from the RAM cell, a read control voltage is applied to the control signal line. The write control voltage is greater than the read control voltage.

Abstract: An auxiliary gasline-heating unit is used in a chemical vapor deposition apparatus. The auxiliary gasline-heating unit serves to increase the exit temperature of the mixture of N2 gas and He-dilute gas in order to prevent TDMAT, Ti[N(CH3)2]4, from being condensed and becoming a gasline contaminant when the mixture mixes with the TDMAT and a carrier gas.

Abstract: A rotatable rack comprising a U-shaped fastening member having a first arm and a second arm each pivotally coupled to first and second L-shaped rods, respectively, by first and second fastening bolts, respectively. The fastening member is fastened onto a wall with a fastening seat and each of the arms is provided with a sunken hole having an inner threaded section. Each fastening bolt includes an outer threaded section at one end thereof which is threadably engaged with a respective one of the inner threaded sections. Each L-shaped rod is provided with a fitting hole at one end portion thereof in which the other end of a respective one of the fastening bolts is fitted into.

Abstract: The invention is directed to a sieving apparatus for a bio-chip, which has a light source, a HOE unit, a splitter, an objective lens, a filter, and an optical signal sensor. The HOE unit is coupled with a light source, so as to diffract the light into a zeroth order beam and a first order beam. The zeroth order beam has no deflection but the first order beam has a deflection from the zeroth order beam. The splitter is coupled to the HOE unit, so as to lead the two beams to the objective lens, which further leads the two beams to the bio-chip, in which the first order beam is incident onto the bio-chip from an incident angle, causing a florescent light from the sample. The bio-chip also reflects the zeroth order beam. Both the reflected zeroth order beam and the fluorescent light travel through the objective lens and the splitter. The filter is coupled to the splitter, so that an undesired portion of the light beams incident on the splitter is filtered.

Abstract: A fabrication process for a lower electrode of a memory capacitor, which process is performed on a substrate already having a first insulating layer formed thereon. First, a self-aligned contact opening is formed in a first insulating layer. The self-aligned contact opening exposes a conducting area on the substrate. A conformal first conductive layer is formed on the first insulating layer and in the self-aligned contact opening, the bottom of which functions as a contact. Then, the self-aligned contact opening is filled with a second insulating layer. The first conductive layer is back etched so as to remove completely the first conductive layer that is outside the self-aligned contact opening, and to remove to a certain depth the first conductive layer that is inside the self-aligned contact opening. A second conductive layer is then formed on the sidewalls of the first and second insulating layers that are located inside the self-aligned contact opening.

Abstract: A fabrication method for a dual damascene structure is described wherein a substrate covered by a HSQ layer is provided. An E-beam curing is conducted on the HSQ layer where the via hole is to be formed. Photolithography and etching are further conducted on the HSQ layer to form a trench. Since the E-beam cured HSQ layer and the thermally cured HSQ layer have a high etching selectively ratio, the HSQ layer that has not been E-beam cured can be wet etched to from a via hole. A dual damascene structure is formed after filling the trench and the via hole with a conductive material, wherein either the via hole or the trench can be first formed.

Abstract: A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.

Abstract: A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit. The cache hit/miss judging circuit is used to judge whether a currently-read address coming from a bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address. The address queue register directly stores the index address of the currently-read address plus a corresponding first one-bit flag signal if the cache hit/miss judging circuit judges that the currently-read address is of cache hit. The prefetch condition judging circuit is used to judge whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss.

Abstract: A method for improving the quality of a deposited layer over a silicon substrate in a selective deposition where the silicon substrate has a native oxide layer thereon. A plasma reaction using a halogen compound as a reactive agent is performed so that the native oxide layer is transformed into a silicon halide layer and then removed at low pressure. A layer of the desired material is formed over the native oxide free silicon substrate surface by selective deposition.

Abstract: An integrated circuit (IC) mounting board is provided for use to mount an IC module and as least one bypass capacitor thereon. The IC mounting board allows the layout of the wiring between the IC module and the circuit lines on the IC mounting board to be more convenient to carry out. Moreover, the IC mounting board allows the bypass capacitor to provide the bypass effect more effectively.

Abstract: A method is used to form a borderless via in a semiconductor device. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first mask layer are formed on a dielectric layer in sequence. The BPSG layer is patterned into a BPSG plug while using the patterned first mask layer as a mask. A second mask layer is formed to cover the patterned first mask layer and the metal layer. The conductive layer is defined to form a conductive line beneath the BPSG plug and the second mask layer. The first and second photoresist mask layers are removed. An inter-metal dielectric layer is formed around the BPSG plug and the conductive line. A via is formed in the inter-metal dielectric layer by removing the BPSG plug. A barrier layer and a metal layer fill the via to form a metal plug.

Abstract: A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed.

Abstract: Provided is an analog-to-digital level error automatic calibration circuit according to the invention. The analog-to-digital level error automatic calibration circuit includes a calibration switch circuit, an input buffer circuit, an error differential amplifying circuit, an N-bit analog-to-digital converter, a calibration register and a subtractor. The differential amplifying circuit receives and amplifies an external sense voltage or a calibration voltage so as to generate a first error amplifying voltage or a second error amplifying voltage. The first and second error amplifying voltages are converted to a first digital value and a second digital value, respectively. Thereafter, the second digital value is subtracted from the first digital value by the subtractor to generate a converted value without taking an offset voltage of an operational amplifier into calculation.

Abstract: An illumination device and an image projection apparatus having the same. The illumination device has a light source with multiple light emitting devices and an uniform illuminating means evenly distributed in front of the light source. The light emitted from the light source can thus uniformly project on a light valve. In addition, a polarization converter is used to convert the light into a usable polarization type, so as to increase the illumination efficiency. The image projection apparatus basically has three of the above mentioned illumination devices to emit three elementary color lights projecting onto a screen.

Abstract: A self-calibrating circuit of a high speed comparator, having a first negative phase logic switch, a second negative logic switch, a first positive phase logic switch, a second positive phase logic switch, a third negative phase logic switch, a fourth negative phase logic switch, a third positive phase logic switch, a fourth positive phase logic switch, a fifth positive phase logic switch, a first current source circuit, a second current source circuit and a control logic circuit. Using the first and the second current source circuits, a self-calibration can be performed while the high speed comparator is just turned on, so that the input offset voltage of the high speed comparator can be eliminated.

Abstract: The invention provides a method for decreasing endpoint detection noise in a chemical-mechanical polishing process. In this method an anti-reflective layer is formed on the material whose reflected light interferes with the incident light. The anti-reflective layer can avoid light reflected by the material that would affect the detector. Thus, the end point of the chemical-mechanical polishing process can be easily verified and the quality of the devices is improved.

Abstract: An electrostatic discharge (ESD) protection circuit. A first NMOS transistor has a source and a gate terminal connected to a ground voltage and a drain terminal connected to the I/O pad. A second NMOS transistor has its source terminal connected to the I/O pad, its drain terminal connected to a voltage source and its gate and substrate terminal connected to the ground voltage. A first PMOS transistor has its drain terminal connected to the ground voltage and a substrate terminal of the first NMOS transistor, its gate terminal connected to the voltage source and its source and substrate terminal connected to the I/O pad. A second PMOS transistor has its source and gate terminal connected to the voltage source, its drain terminal connected to the I/O pad and its substrate terminal connected to a drain terminal of the second NMOS transistor.

Abstract: The invention described a thermal printer. The thermal printer has a supply reel, a take-up and a pair of motors. Each motor connects with the supply reel and the take-up reel, respectively. A detecting apparatus detects ribbon and the reel parameters while initializing the thermal printer. A memory stores a transforming table which can obtain the driving pulse width of each motor from a radius of the supply reel, a radius of the take-up reel and the ribbon tension. A control apparatus drive each motor with different pulse width according to parameters detected by the detecting apparatus and the transforming table. A thermal print head performs a printing process.