Abstract: A method of updating parameters for pixels associated with a background estimation portion of a video frame is disclosed. The method comprises receiving a group of pixels of an incoming data stream associated with the video frame, each pixel of the group of pixels being characterized by a plurality of parameters; comparing, for each pixel of the group of pixels, the plurality of parameters for a pixel with the plurality of parameters for adjacent pixels; determining, for each pixel of the group of pixels, whether the parameters are similar to the parameters of an adjacent pixel; identifying a region of the group of pixels having similar parameters; and updating parameters for all pixels associated with the region with a single set of parameters.

Abstract: A method of operating an input/output interface is described. The method comprises eliminating a current path into an output pin of an input/output interface while the input/output interface receives an operational power signal during a first mode of operation; and enabling the current path into the output pin of the input/output interface to limit a voltage magnitude externally applied to the output pin of the input/output interface during a second mode of operation.

Abstract: A method of implementing output ports of a programmable integrated circuit is disclosed. The method comprises coupling control signals to predetermined output ports of the integrated circuit; setting, by the control signals, initial output values of the predetermined output ports during programming of the programmable integrated circuit; and enabling normal operation of the predetermined output ports after the programming of the programmable integrated circuit. An integrated circuit having programmable output ports is also disclosed.

Abstract: A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.

Abstract: An integrated circuit enabling asynchronous data communication is disclosed. The integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising programmable resources; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block of the plurality of circuit blocks synchronously processes data received from the routing network. A method of routing data in an integrated circuit is also disclosed.

Abstract: A method and circuit for providing temporal redundancy for a hardware circuit implemented in an integrated circuit is disclosed. The method comprises implementing a comparison circuit for comparing values in the integrated circuit; coupling an input signal to the hardware circuit; detecting an output signal of the hardware circuit at a first time, wherein the output signal is based upon the input signal; holding the input signal until at least a second time; detecting the output signal of the hardware circuit at the second time; determining, by the comparison circuit, whether the output signal of the hardware circuit at the first time corresponds to the output signal of the hardware circuit at the second time; and generating an error signal based upon determining whether the output signal of the hardware circuit at the first time corresponds to the output signal of the hardware circuit at the second time.

Abstract: A method of generating parameters for a predistortion circuit in an integrated circuit using a matrix is disclosed. The method comprises storing a first column of a first matrix; generating the remaining columns of the first matrix based upon the first column of the matrix; generating a plurality of rows of a second matrix by performing a first set of calculations; and generating the remaining rows of the second matrix by selectively shifting the first rows of the second matrix.

Abstract: A configurable memory map interface coupled to a circuit element having input/output ports is disclosed. The configurable memory map interface comprises an input coupled to receive an address enabling reading from or writing to the circuit element; a memory storing enable signal parameters, the enable signal parameters controlling timing of enable signals for the reading from or the writing to the circuit element; and an enable signal generator generating the enable signals enabling the reading from or the writing to the circuit element based upon the enable signal parameters stored in the memory. A method of implementing a configurable memory map interface is also disclosed.

Abstract: A circuit for receiving a sample of an input signal to be used to calculate parameters for a predistortion circuit in an integrated circuit is described. The circuit comprises a power measurement circuit coupled to receive the input signal; a first port of a dual port random access memory for receiving data associated with power of the input signal over a predetermined period of time; and a second port of a dual port random access memory for generating the data associated with the power of the input signal stored over the predetermined period of time. A method of receiving a sample of an input signal to be used to calculate parameters for a predistortion circuit in an integrated circuit is also described.

Abstract: A method of accepting a sample of an input signal to be used to calculate parameters for a predistortion circuit in an integrated circuit is disclosed. The method comprises accumulating data associated with an input signal over a period of time; detecting the sample of the input signal at a predetermined time; comparing the sample of the input signal to the accumulated data; and determining whether the sample of the input signal is acceptable to be used to calculate parameters for the predistortion circuit. A circuit for accepting a sample of an input signal to be used to calculate parameters for a predistortion circuit in an integrated circuit is also disclosed.

Abstract: A method of placing clock circuits in an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the integrated circuit; identifying portions of the circuit design comprising clock circuits; determining an order of clock circuits to be placed based upon resource requirements of the clock circuits; and placing the portions of the circuit design comprising clock circuits in sites of the integrated circuit. A system for placing clock circuits in an integrated circuit is also disclosed.

Abstract: A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock is disclosed. The circuit comprises a plurality of data recovery circuits, each data recovery circuit coupled to receive a corresponding data stream of the plurality of data streams and having a phase shifter generating a clock signal used to receive the data stream; and a channel deskew circuit coupled to receive the output of each data recovery circuit and the pixel clock. A method of receiving video data is also disclosed.

Abstract: A method of placing a circuit design in logic blocks of an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the logic blocks of the integrated circuit; determining clock skew for a clock tree providing clock signals to a plurality of memory elements of the integrated circuit; evaluating timing requirements associated with the circuit design; and transforming the circuit design to a placement configuration, wherein the placement configuration places the circuit design in the logic blocks of the integrated circuit according to the timing requirements of the circuit design and the clock skew for the clock tree.

Abstract: An integrated circuit device having a multi-layer substrate coupled to receive an integrated circuit die and enabling fixed voltage reference signals of a power distribution network and input/output signals to be routed in the integrated circuit device. The multi-layer substrate comprises a first metal layer comprising a reference signal plane of coupling a first fixed voltage reference signal; a dielectric layer positioned on the first metal layer; and a second metal layer having a plurality of conductive traces, wherein the plurality of conductive traces comprise conductive traces for coupling a second fixed reference signal and input/output signals. The plurality of conductive traces may be in a predetermined pattern having reference signal traces and input/output signal traces. A method of enabling different signals comprising reference signals and input/output signals to be routed in a multi-layer substrate adapted to receive a die in an integrated circuit is also disclosed.

Abstract: A method of implementing a circuit design is described. The method comprises specifying criteria for control and data path identification; generating a representation for the circuit design; analyzing the representation based upon the criteria for control and data path identification; identifying control and data elements of the circuit design based upon paths and macros of the circuit design; and generating a modified representation, by a computer, for the circuit design based upon the identified control and data elements.

Abstract: According to various embodiments of the present invention, an intelligent framer/mapper integrates the framer, mapper, and the controlling function of the host processor, implemented as either a soft processor or an embedded processor, into a single device, such as a programmable logic device. The use of the soft processor or embedded processors on the device reduces the load on the host processor on the line card. According to some aspects of the invention, the devices takes advantage of an embedded, dedicated processor and/or soft processor(s) to allow for a distributed processing on a single chip.

Abstract: Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a first inverter comprising a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; a second inverter comprising a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the second node being coupled to a control terminal of the second transistor. The memory array further comprises a third inverter and a fourth inverter.

Abstract: A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.

Abstract: A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.