Abstract: A circuit for determining a process corner for a CMOS device of an integrated circuit is disclosed. The circuit comprises a CMOS monitoring circuit comprising an NMOS transistor and a PMOS transistor of the integrated circuit; reference circuit comprising elements for generating a reference voltage for an NMOS transistor and a reference voltage for a PMOS transistor; a first comparator for comparing a voltage generated by the NMOS transistor monitored by the CMOS monitoring circuit with the reference voltage for a NMOS transistor; and a second comparator for comparing a voltage generated by the PMOS transistor monitored by the CMOS monitoring circuit with the reference voltage for a PMOS transistor. A method for determining a process corner for CMOS devices of an integrated circuit is also disclosed.

Abstract: A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.

Abstract: A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page of data in a block of random access memory; determining a page fault while interfacing with the block of random access memory when implementing the circuit design; performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and accessing the second page of data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Abstract: A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for programming the blocks of memory. The circuit also includes a directory of locations for defective memory cells of blocks of memory, where the directory of locations is common to the blocks of memory for storing locations of defective memory cells of the blocks of memory. Methods of repairing defective memory of an integrated circuit are also disclosed.

Abstract: A method of generating a random number using a multiplier oscillation, the method comprising providing a multiplier circuit coupled to receive a first digital input and a second digital input, wherein the first digital input and the second digital input are asynchronous signals and the first digital input comprises a feedback signal based upon an output of the multiplier circuit; allowing the multiplier to enter a state of feedback oscillation; and generating a random number based upon the output of the multiplier circuit. The method may further comprise providing a plurality of adders receiving feedback signals.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Abstract: A method of providing intensity correction for a video is disclosed. The method may comprise evaluating a portion of a frame of the video; determining a difference in intensity of a current block of the frame with the corresponding block of the previous frame; correcting all blocks of the frame with local intensity correction if a first set of parameters is met; and correcting the current block of the frame with both global intensity correction and local intensity correction if the first set of parameters is not met. An integrated circuit having a circuit for providing intensity correction for a video is also disclosed.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.

Abstract: A method of enabling the generation of reset signals in an integrated circuit is disclosed. The method comprises receiving information related to reset ports for a plurality of intellectual property cores in a design tool; providing an intellectual property core comprising a reset logic circuit adapted to generate a plurality of reset signals for the plurality of intellectual property cores; and generating, by the design tool, configuration data enabling programmable interconnects to couple a first reset signal of the plurality of reset signals to a first intellectual property core of the plurality of intellectual property cores and a second reset signal of the plurality of reset signals to a second intellectual property core of the plurality of intellectual property cores.

Abstract: A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers coupled to receive input data; an arithmetic function circuit having a plurality of arithmetic function elements, each arithmetic function element coupled to at least one other arithmetic function element of the plurality of arithmetic function elements and coupled to receive outputs of at least one of the first plurality of input registers and the second plurality of input registers; and an output coupled to the arithmetic function circuit. A method of implementing a configurable arithmetic block in a device having programmable logic is also disclosed.

Abstract: A substrate for an integrated circuit package is disclosed. The substrate comprises a core comprising a first dielectric layer having a first thickness; conductive traces formed on the first dielectric layer for routing signals within the integrated circuit package, wherein the conductive traces have a second thickness; and a substrate support structure comprising conductive traces formed on the first dielectric layer, where the conductive traces of the substrate support structure have a third thickness which is greater than the second thickness. A method of forming an integrated circuit package is also disclosed.

Abstract: A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.

Abstract: A method of configuring a device having programmable logic is disclosed. The method comprises generating a netlist associated with a circuit design; coupling the netlist to the device having programmable logic; performing a re-targeting function using a circuit on the device having programmable logic; generating configuration bits for configuring the programmable logic; and configuring the programmable logic to implement the circuit design according to the configuration bits based upon the netlist and results of the re-targeting function.

Abstract: A method of verifying a triple module redundant circuit. The method comprises providing three circuits, each comprising a redundant circuit; coupling a feedback voter circuit at the output of each circuit of the three circuits, each feedback voter receiving the output of each of the three circuits; disabling a first circuit of the three circuits; enabling the first circuit; disabling a second circuit of the three circuits; and verifying the output of the triple module redundant design to determine whether an error has occurred. A article of manufacture for verifying a design implemented as a triple redundancy module is also described.

Abstract: An integrated circuit having a plurality of data transceivers positioned on opposite ends of the integrated circuit is disclosed. The integrated circuit comprises a first plurality of data transceivers positioned in a column on a first end of the integrated circuit and a second plurality of data transceivers positioned in a column on a second end. A circuit is preferably positioned between the first plurality of data transceivers and the second plurality of data transceivers. The circuit could comprise, for example, circuits for implementing a programmable logic device. The circuitry of the plurality of data transceivers is also preferably arranged such that analog circuitry is positioned closer to an end of the integrated circuit than the digital circuits to reduce interference with the analog circuits. According to another aspect of the invention, the data transceivers are formed on layers to reduce the amount of interference.

Abstract: A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Abstract: A memory array having a plurality of memory cells is disclosed, where each memory cell comprises a first inverter having a first transistor coupled between a reference voltage and a first node for receiving input data and a second transistor coupled between the first node and ground; and a second inverter having a third transistor coupled between the reference voltage and a second node for storing inverted input data and a fourth transistor coupled between the second node and ground, the first node being coupled to control terminals of the third transistor and the fourth transistor and the second node being coupled to control the first transistor and the second transistor; wherein the third transistor is implemented with physical dimensions which make the third transistor stronger than the first transistor, or the second transistor is implemented with physical dimensions which make the second transistor stronger than the fourth transistor.

Abstract: Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

Abstract: A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

Abstract: A molded integrated circuit package is described. The molded integrated circuit package comprises a substrate having a plurality of contacts on a first surface; a die having a plurality of solder bumps on a first surface, the plurality of solder bumps being coupled to the plurality of contacts on the first surface of the substrate; an adhesive material positioned on a second surface of the die; a lid attached to the adhesive material; and an encapsulant positioned between the lid and the substrate. Methods of forming molded integrated circuit packages are also disclosed.