Abstract: A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Abstract: A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Abstract: A method of generating parameters for a predistortion circuit in an integrated circuit is disclosed. The method comprises receiving, at the predistortion circuit, an input signal to be amplified by a power amplifier; receiving an output of the power amplifier at an input of the integrated circuit; comparing an output of the predistortion circuit with the output of the power amplifier; conforming the output of the power amplifier with the output of the predistortion circuit; and generating parameters to be applied to the predistortion circuit based upon the conformed output of the power amplifier and the predistortion circuit. An integrated circuit having a circuit for generating parameters for a predistortion circuit of the integrated circuit is also disclosed.

Abstract: An integrated circuit having a circuit for reducing distortion in a power amplifier is disclosed. The integrated circuit comprises a predistortion circuit coupled to receive a signal to be amplified; sample capture buffers coupled to an output of the predistortion circuit and an input/output port of the integrated circuit; and an estimator circuit coupled to the sample capture buffers, wherein the estimator circuit generates parameters for the predistortion circuit based upon the output of the predistortion circuit and an output of the power amplifier received at the input/output port of the integrated circuit. A method of reducing distortion in a power amplifier is also disclosed.

Abstract: A programmable device having a processing core is configured to use a subset of configuration memory cells as read/write memory. The subset of memory cells is a don't care set that includes configuration memory cells that can be set or reset without modifying the function or behavior of the configured circuits of the programmable device.

Abstract: A method of sampling a frequency difference in an integrated circuit is disclosed. The method comprises the steps of receiving a clock signal in a first clock domain; comparing a count of the clock signal in the first clock domain to a predetermined value N; converting the result of the comparison to a second clock domain; and generating an error signal representing the difference between the count of the first clock signal and the count of a second clock signal in the second clock domain. A circuit for sampling a frequency difference in an integrated circuit is also disclosed.

Abstract: A method of generating a plurality of data streams using a data protocol is disclosed. The method comprises steps of receiving an input data stream comprising a periodic sequence of data words, wherein each the data word of the input data stream is associated with a data stream of a plurality of data streams. The data words of the input data stream are sequentially processed by a data control circuit. Finally, data output by the data control circuit is demultiplexed to generate a plurality of output data streams. A circuit for generating a plurality of data streams using a data protocol is also disclosed.

Abstract: An integrated circuit device is described. In particular, the integrated circuit comprises a substrate comprising active devices; a plurality of metal layers formed over the substrate, the plurality of metal layers being separated by insulating layers; a plurality of vias enabling connections to the active devices of the substrate; a contact pad support structure defining an opening in a metal layer of the plurality of metal layers and being coupled to an interconnect line; and a contact pad formed over the contact pad support structure. A method of implementing a contact pad in an integrated circuit is also disclosed.

Abstract: A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

Abstract: A method of reducing power of a circuit is described. The method includes determining at least one unused selection input associated with stages of a multiplexer tree; pulling the at least one unused selection input to a constant value; and assigning predetermined values to unused data inputs of the multiplexer tree associated with the at least one unused selection input.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: The circuits and methods of the various embodiments of the present invention enable changing the frequency of a frequency synthesizer. According to one embodiment, a method of changing a frequency of a clock signal generated by a frequency synthesizer comprises the steps of receiving a reference clock signal; receiving a command comprising a new frequency synthesizer value; locking to a new frequency based upon the new frequency synthesizer value; and dynamically outputting a generated clock signal based upon the new frequency synthesizer value. According to another embodiment, a method of changing a frequency of a clock signal comprises adaptively adjusting the digital loop bandwidth of the frequency synthesizer. A circuit for changing a frequency of a clock signal generated in an integrated circuit is also disclosed.

Abstract: A method of employing memory cells of an integrated circuit is disclosed. The method comprises steps of storing configuration data in a plurality of memory cells of a memory of the integrated circuit; selecting unused memory cells of the memory of the integrated circuit for use as a scratchpad memory; providing access to the unused memory cells of the integrated circuit; and enabling use of the unused memory cell of the integrated circuit in a user mode as scratchpad memory. According to one embodiment of the invention, a plurality of input/output ports of the integrated circuit is coupled to a plurality of JTAG inputs coupled to the plurality of unused memory cells. A programmable logic device having memory cells for storing data, and a circuit employing a programmable logic device, are also disclosed.

Abstract: A method of enabling variable latency data transfers in an electronic device, such as an FPGA with an embedded processor, is described. According to one aspect of the invention, a method comprises steps of providing an address for a data transfer between a memory controller and a peripheral device; coupling an address valid signal to the peripheral device; transferring the data between the memory controller and the peripheral device; and receiving a data transfer complete signal at the memory controller. According to another aspect of the invention, an integrated circuit enabling a variable latency data transfer is described. The integrated circuit comprises peripheral device; a memory controller coupled to the peripheral device; an address valid signal coupled from the memory controller to the peripheral device; and a transfer complete signal coupled from the peripheral device to the memory controller.

Abstract: A method of processing data input to a first-in first-out memory is disclosed. The method comprises steps of receiving input data words from a pipeline stage at an input of the first-in first-out memory; receiving data valid bits associated with the pipeline stage; generating a count associated with the data valid bits; and coupling the count to the first-in first-out memory. The step of generating a count associated with the data valid bits may comprise encoding the data valid bits to generate a valid data word representing the number of pipeline stages having valid data. The method of further comprises a step of generating an almost full signal based upon the count, and in particular generating an almost full signal when a read pointer incremented by the count of valid bits in the pipeline stages equals a write pointer. A circuit for processing data is also disclosed.

Abstract: Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices having a defective portion of programmable blocks; identifying, for each programmable device which is identified to have a defective portion of programmable blocks, a location of the defective portion; and storing, for each programmable device which is identified to have a defective portion of programmable blocks, the location of the defective portion on the programmable device.

Abstract: The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method comprises the steps of coupling test equipment to the integrated circuit; coupling a test equipment clock signal from the test equipment to the integrated circuit, wherein the test equipment clock signal has a first frequency; generating an internal burst clock signal within the integrated circuit based upon the test equipment clock signal, wherein the internal test clock signal has a burst frequency; and testing the integrated circuit using the internal burst clock signal. Other methods and circuits for testing programmable logic devices are also described.

Abstract: A method of configuring a device having programmable logic is disclosed. The method comprises storing instructions in the device; selecting between one of the instructions stored in the device and an instruction coupled to an input/output port of the device; coupling the instruction to a non-volatile memory; and reading a configuration bitstream from the non-volatile memory based upon the selected instruction. A method of enabling a multi-boot configuration of a device having programmable logic is disclosed. The method comprises powering up the device using a first configuration bitstream from a first type of configuration device in response to a first command; receiving a reboot command; and reconfiguring the device using a second configuration bitstream from a second type of configuration device in response to a second command which is different than the first command. Circuits enabling a multi-boot configuration of a device having programmable logic are also disclosed.

Abstract: A method of generating an output of a frequency synthesizer is disclosed. The method comprises the steps of generating an output of the frequency synthesizer based upon frequency synthesizer values and a reference clock signal; receiving a command comprising a first new frequency synthesizer value; locking to a new frequency based upon the first new frequency synthesizer value; and simultaneously loading a second new frequency synthesizer value while locking to the new frequency. A circuit for generating an output of a frequency synthesizer is also disclosed.

Abstract: Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a stream of data in response to a clock signal in a first clock domain. A second circuit coupled to the first circuit receives the stream of data from the first circuit in response to a low level of an empty signal in the second clock domain. A comparator circuit coupled to receives the stream of data and the output of the second circuit. Specific applications to dual port RAMs as well as implementations in a programmable logic devices are disclosed. Various methods of testing an asynchronous data transfer are also disclosed.